To assist relevant departments in better understanding the online public opinion regarding graduate employment, a system for analyzing online public sentiment during the job-seeking period of college graduates has been developed using big data and artificial intelligence technologies. The system is based on the BERT model and collects data from social media using web crawling techniques. After preprocessing the collected data, a sentiment analysis model is trained using deep learning. The model is then integrated into the online public opinion analysis system using front-end and back-end technologies, combining the training results of the model. Currently, the system has been completed and has passed the review of relevant departments. It is about to be put into use, with the expectation of playing a role in overall public opinion control and guidance objectives.

In view of the problems that the reliability of board-level installation is not considered in the design of CQFP devices in the early stage, such as the large coplanarity difference between leads and porcelain, and the insignificant stress release effect of leads, taking CQFP128 devices as an example, the lead molding design and board-level reliability verification are studied. The material structure, wiring mode and lead forming requirements of CQFP are analyzed in detail, and it is proved by experiments that the formed device has better welding coplanarity. After the vibration test of the whole machine, the reliability of the solder joint is characterized by X-ray, scanning electron microscope and other analysis methods. The study can provide reference for lead forming and reliability verification of similar devices.

To meet the application requirements of ADC in high-precision conversion and multiplexing scenarios, a two-step incremental Sigma-Delta ADC circuit with chopper stabilization is proposed. The design eliminates quantization noise by adding a conversion stage through hardware reuse to quantize residual voltage, and applies chopper stabilization technique to the first-stage integrators of both conversion stages to reduce the impact of op-amp offset voltage. Simulation results show that under conditions of 1 kHz signal bandwidth, 1.8 V power supply, and input normalized sine wave amplitude of 0.6, the ADC achieves a signal-to-noise ratio of 103.6 dB with an effective number of bits of 16.92, making it suitable for multi-sensor multiplexing and high-precision conversion applications.

This paper investigates the effect of strain engineering on the quantum transport properties of phosphorene. Based on the research background and application prospects of phosphorene in flexible electronic devices, first-principles calculations were employed to systematically study the strain modulation mechanism of phosphorene. By establishing electronic transport models under different strain conditions, the influence patterns of strain on band structure, electron density, and density of states were analyzed, thus verifying the significant anisotropic characteristics exhibited by phosphorene under strain in different directions. This research provides a theoretical foundation for the application of phosphorene in flexible electronics and sensors, confirming the important role of strain engineering in modulating the electrical properties of phosphorene.

Aiming at the problems of low sensitivity and long response time of non-dispersive infrared CH₄ gas sensor, a CH₄ gas sensor based on photoconductive principle is designed. The sensor is mainly composed of PbSe photoconductive infrared detector, signal processing circuit, light source driving circuit and light path gas chamber. By analyzing the relationship between gas concentration and detector output signal, the concentration output relationship equation is fitted to realize the detection function. Through experiments, gases with different concentrations are detected at room temperature. The results show that the output error, minimum detection limit, minimum response time and other parameters of the sensor are good, and the gas can be effectively measured in the range of 1000 cm³/m³.

To reduce the impact of offset voltage and noise on traditional bandgap references, a low temperature drift, low noise, high-precision voltage bandgap reference is proposed using SMIC 40 nm CMOS process. Temperature coefficient modulation resistors and output voltage divider resistors are trimmed using resistor matrices to minimize the process impact on temperature coefficient and bandgap reference voltage. Chopper modulation combined with a low-pass filter is employed to significantly reduce the influence of offset voltage and noise on the reference voltage. Simulation using Cadence Spectre tools shows that with a 3.3 V power supply under typical conditions, the temperature coefficient of the output voltage is 5.87×10^-6/℃ over a temperature range of -40 ℃ to 125 ℃. After incorporating the chopper circuit, noise is significantly reduced compared to ordinary bandgap references, and relative accuracy is improved by 50 times.

To address the low-frequency noise interference issue in programmable gain instrumentation amplifiers(IAs) for sensor AFEs, a low-noise programmable gain chopper current-feedback IA is designed. The design employs chopper technology to suppress low-frequency noise, exemplified by 1/f noise. A digital-to-analog converter(DAC) is incorporated to implement sensor offset compensation using current stacking, resolving the issue of performance degradation caused by sensor offset. A programmable resistor network is employed to achieve programmable gain amplification, enhancing the IA's versatility. The IA is based on TSMC's 0.18 μm process, with a supply voltage of 2.7~3.6 V. By adjusting the resistor network, a gain of 16~2048 can be achieved. Additionally, it is also ideal in sensor offset compensation range and equivalent input reference noise parameters.

Aiming at the problem that the traditional dynamic element matching(DEM) method needs more hardware resources, a second-order error feedback noise-shaping SAR ADC is designed. The design uses segmented capacitors to reduce the size of DAC array and the capacitance of error feedback loop, and reduce the area of the whole circuit. On this basis, a DEM method applied to segmented capacitor array is formed, which reduces the influence of capacitor mismatch on performance parameters such as signal-to-noise-distortion ratio(SNDR) at the cost of fewer additional circuit components. The simulation results show that the designed noise-shaping SAR ADC can achieve 70.9 dB SNDR with an 8-bit capacitor array with a capacitance mismatch of 0.3%, and the required area is only 0.019 mm².

Based on the excellent microwave characteristics of flexible liquid crystal polymer substrate, this paper designs and implements a miniaturized triple-band bandpass filter. Through the adoption of three-dimensional layout in multilayer LCP substrate and innovative use of vertical spiral inductors and vertical interdigital capacitor structures, the miniaturization of the filter is achieved. The research focuses on analyzing key technologies of multilayer spiral inductor design and vertical interdigital capacitor design, with an in-depth discussion on the effects of defected ground structures. Test results show that the filter features small size and excellent performance, with high consistency between measurement and simulation results, providing a new technical solution for the development of miniaturized communication systems.

Based on the investigation of existing products, a design scheme of smart home control system is proposed. The design adopts STM32 as the main node and is equipped with Wi-Fi network module to realize the communication between the main controller and Android application. With the help of MQTT protocol, data transmission and message processing are carried out. Through the LVGL graphic UI library installed in the touch screen of LCD serial port, a concise interactive interface is realized, so that users can control household equipment more conveniently. Various sensor technologies are used to collect indoor environmental data in real time and process and analyze them. The design can set different intelligent control strategies for different application scenarios in different time periods, realize automatic home control, and ensure the data and privacy of users by using data encryption and user authentication. The system gives full play to the advantages of modular design and has a good price-performance ratio.

Intelligent human-machine interaction systems enabled by flexible electronics demonstrate superior flexibility and adaptability compared to traditional electronic devices, meeting diverse requirements of human-machine interaction. This paper aims to comprehensively review the current research status of flexible electronics in intelligent human-machine interaction systems, thoroughly analyze the advantages of flexible electronics in the field of human-machine interaction, while summarizing and identifying the opportunities and challenges of flexible electronics in human-machine interaction. Furthermore, it looks into the future development trends of intelligent human-machine interaction systems enabled by flexible electronics, providing solid theoretical guidance for subsequent technological development and practical applications.

In order to solve the problem that the production cost of integrated circuits increases with the progress of semiconductor manufacturing technology, especially for the problems of large area, high power consumption and poor stability of resistors, capacitors and operational amplifiers in traditional analog architecture DC/DC converters, a buck DC/DC converter based on digital PWM modulation is designed. The design is based on CSMC 0.18 μm BCD process, and the digital PID compensator is designed with Verilog hardware description language, which is verified by simulation in the mixed simulation environment of VCS+XA. The simulation results show that the output ripple is low and the output voltage is stable under different PVT conditions and different loads, and the design goal of low cost and high robustness is realized.

This study addresses the issue of significant memory resource consumption caused by the traditional lookup table method when frequently computing the arctangent function in applications such as image processing, electronic compasses, and navigation control systems. An improved solution based on the CORDIC algorithm is proposed. By increasing the iteration clock frequency and performing one iteration on both the rising and falling edges of the clock, the computational speed is doubled. Additionally, the algorithm supports adjustable calculations for both q1.15 and q1.31 data formats, significantly reducing hardware resource consumption. Simulation results demonstrate that the improved algorithm ensures computational accuracy while effectively enhancing speed and providing data format flexibility, offering a more efficient solution for related applications.

To enhance user experience by reducing the computational complexity of background removal methods in real-time image recognition, a lightweight background removal method based on channel calculations is proposed. The study revolves around the concept and related properties of channel calculations. By utilizing the relationship between the channels of a color image, the selection of target pixels can be achieved through simple arithmetic and relational calculations, avoiding the use of more complex computational forms such as spatial distance formulas and gradients. This effectively reduces computational complexity. Both theoretical and experimental results demonstrate that under application scenarios where the foreground main color is single, the proposed method can select target pixels with low computational complexity and efficiently achieve background removal. This can contribute to improving user experience in real-time intelligent applications related to image processing.

Aiming at the equalization protection of lithium batteries, a voltage sampling circuit based on the equalization protection chip for lithium batteries is designed. The lithium battery equalization protection adopts the active equalization method. The voltage sampling circuit samples the voltage of two lithium batteries to monitor the difference between lithium batteries, and converts the data through an 8-bit successive approximation digital-to-analog converter. The equalization control logic is used to analyze the converted data and performs equalization protection for the lithium battery. The HHNEC 0.18μm BCD process is used for the design and verified by simulation. Simulation results show that the voltage sampling circuit has high voltage sampling accuracy, and the effective number of bits of the successive approximation type digital-to-analog converter and other indicators have excellent performance. It can reliably sample the voltage of each battery and is suitable for the application of lithium battery equalization protection chip, which is conducive to prolonging the use of battery packs.

In view of the critical role of analog-to-digital converter(ADC) in the field of chip and mixed-signal processing, a sigma-delta ADC based on Mash2-1 cascade architecture is designed to explore the possibility of further improving the accuracy of ADC and meet the new requirements of contemporary application systems. TSMC 180 nm CMOS process is adopted in the design. While completing the modulator circuit, Verilog code is used to realize the matching error elimination and digital decimation filter. The modulator is modeled and the non-ideal factors are analyzed, and the non-ideal of the circuit is optimized by using chopper modulation technology. The simulation results show that the design has excellent signal-to-noise ratio and ideal performance indexes such as total harmonic distortion under 3.3 V power supply, 27 ℃ working environment and TT typical process conditions, and is suitable for high-precision and low-distortion applications.

To achieve higher signal-to-noise ratio and area efficiency with limited hardware overhead, a dynamic zoom ADC based on time-division multiplexed SAR ADC is proposed. Meanwhile, a passive implementation scheme for extracting coarse quantized analog residues and feedforward is proposed, which does not require the design of an active summing operational amplifier, avoids the attenuation of common passive summing signals, and reduces the "fuzz" caused by coarse quantization noise leakage. The overall circuit is designed in two parts:coarse quantization and fine quantization. Coarse quantization is realized by a 3 bit asynchronous SAR ADC, and fine quantization is realized by a second-order 3 bit sigma-delta mo-dulator. Based on 0.18 μm CMOS technology, 3.3 V supply voltage, 1 MHz sampling frequency, and 1 kHz bandwidth, the current consumption is 76 μA, and the specific values of signal-to-noise distortion ratio and FOM are obtained, verifying the feasibility of the design.

Based on the existing products, a high-precision, low-noise and low-dropout linear voltage regulator circuit is designed. A folded cascode amplifier is designed to reduce noise and improve gain. The PMOS transistor is used to replace the resistor in the overheat protection circuit, which reduces the power consumption. At the same time, the gate drive structure and current control mode are used to realize the turn-on and turn-off of the switch tube. Based on TSMC 0.35 μm BiCMOS process and Cadence software, the design, layout drawing and pre- and post-simulation are carried out, and the relevant parameter values are obtained in the post-simulation. The parameters are analyzed in detail, and the power supply voltage rejection ratio at different frequencies is compared. The experimental results show that the design has achieved the design goal of high precision and low power consumption.

Aiming at the problem of deterministic delay in stability, reliability and repeatability of high-speed analog-to-digital converter JESD204B interface multi-chip synchronization system, a solution scheme is proposed. Based on the synchronization principle of subclass 1, the scheme can automatically correct the repeatable deterministic delay by automatically correcting the setup and hold time of reference clock relative to the device clock and using the deterministic delay principle. The technology of adjustable SYSREF delay and automatic correction of internal detection mechanism of analog-to-digital converter is adopted to determine the optimal delay time and realize fixed phase sampling of multi-chip analog-to-digital converter. At the receiving end of the programmable logic chip, the relative position of data arrival with the local multi-frame clock is automatically corrected, thus establishing a stable and repeatable deterministic delay. The design is helpful for multi-chip synchronization system to better cope with harsh environment and self-sensitive delay changes.

In many fields, the mode of FPGA debugging and programming using traditional USB-JTAG interface is greatly limited, for example, due to the long transmission distance, the debugging interface is sealed by the shell and other reasons, it can not operate normally, and each operation can only be directed at a single FPGA, which is inefficient. To solve the problems, a remote debugging and programming system of FPGA based on 32-bit MCU is proposed. The design realizes the remote debugging and programming functions of FPGA through Ethernet. The main control chip is integrated on the FPGA board, and is connected with the FPGA through JTAG and SPI interfaces, and the other end is connected with computer equipment through Ethernet to realize remote debugging and programming functions. The design increases the convenience of FPGA debugging, improves the efficiency of programming, and has strong expansibility.

The application and performance of FDD LTE/NR Dynamic Spectrum Sharing technology in 5G networks is investigated in the study, which focuses on the 1.8 GHz band and conducts experimental tests in an indoor environment. Using drive tests and CQT methods, the study compares network performance under LTE-only, NR-only, and DSS modes. The performance of dynamic spectrum sharing is validated from multiple dimensions, including RSRP, SINR, MCS, occupied RB numbers, and throughput. Results show that while DSS technology improves spectrum utilization, it impacts both LTE and NR performance. LTE performance loss ranges from 3% to 8%, while NR performance loss is between 10% and 22%. DSS technology can flexibly adjust resources based on LTE and NR service demands, and in the context of increasing 5G terminal penetration and network development, can effectively enhance network capacity and spectral efficiency.

Aiming at the slow speed of traditional comparators， a high-speed comparator with optional speed is proposed. The comparator applies a rail to rail input structure. The pre-amplification circuit of the high-speed comparator is composed of a two-stage differential amplifier， and the result of the amplifier is fed into a latch circuit to get the comparison result. The latch circuit reduces the comparator delay and increases the comparator speed . In the comparator circuit， a comparator reverse input mode selection circuit， a comparator speed mode selection circuit， a comparator output stage selection circuit， and a comparator lag terminal selection circuit are added. The reverse input of the comparator has eight selection modes， the speed of the comparator has four selection modes， and the lag end of the comparator has four selection modes. The rail-to-rail input structure of the comparator circuit can detect differential mode voltage of 2mV. A multifunctional comparator with rail to rail， optional speed and optional hysteresis end is realized.

Aiming at the problems existing in the field test of industrial control buses in engineering monitoring, in order to simplify the carrying capacity of equipment and improve the adaptability of monitoring to complex application scenarios, a data integrated monitoring system based on FPGA, connected to the upper computer through PCIe and supporting IIC and SPI buses is proposed. Firstly, the overall design of the integrated monitoring system is given, and then the detailed design schemes of hardware and logic are given according to the principles of hardware reconfigurablity and software field definition. Eight paths of IIC and SPI are designed to meet the problem of excessive industrial monitoring equipment. Hardware interfaces are reduced and software protocol options are increased. According to the requirements, the top-down design module is analyzed and divided to complete the code design. According to the fault-tolerant ability, the monitoring and fault injection functions are designed, the board-level debugging is carried out, and the upper computer test is finally completed. The results show that the designed communication board is qualified and passed the overall verification.

Traditional Dickson structure charge pumps suffer from slow rise times, which can hinder the performance of antifuse FPGAs in user mode and lead to timing issues. To address these limitations, a rapid-boot charge pump circuit is proposed, building upon the traditional Dickson structure. The enhanced design incorporates a clock signal enhancement circuit and a 0 V generation circuit alongside the standard oscillator, non-overlapping clock generation circuit, and main charge pump circuit. The clock signal en- hancement circuit expedites charge transfer, enabling rapid charge pump boost. The 0 V generation circuit effectively isolates the high-voltage module from the low-voltage module, providing circuit protection during programming mode. Simulation experiments conducted under global equivalent load conditions, based on CMOS technology, demonstrate that the improved charge pump achieves a stable output 57.6% faster than the original design. Actual chip fabrication and circuit function testing confirm the successful implementation of the proposed design.

To address the issue of multipath fading in radio monitoring, which causes signal strength fluctuations and reduces localization accuracy, this paper proposes an interference source localization method based on a wireless sensor network. The method first employs regional segmentation clustering to determine the number of interference sources and divide the monitoring area. Sensor nodes are then used to collect signal strength, frequency distribution, and correlation coefficients, while time-stamp information is utilized to calculate signal transmission distances. Finally, real-number encoding and crossover recombination optimize the sensor node population, solving the fitness function to obtain the optimal localization path and effectively avoid severe multipath effect regions. Experimental results demonstrate that the proposed method reduces average localization errors by 11.1% and 9.6% compared to the air-ground cooperative and 3D display methods, respectively, while improving localization speed by 34.4% and 47.3%. Additionally, it achieves an interference source recognition rate exceeding 90%, significantly enhancing localization accuracy and efficiency in complex environments.

In order to solve the problems of high loss, short service life, poor anti-vibration ability and low reliability of the existing incremental encoder controlled by shaft handle, a design scheme of incremental photoelectric encoder with optical-mechanical-electrical integration is introduced, including innovative designs such as 32-inner petal shaft sleeve and retractable ball positioning, Z-shaped light-shielding disc design and infrared photosensitive OC open-circuit output circuit. Through precise struc-tural design and material selection, high-precision 32-gear electrical signal conversion is realized. The structural reliability is verified by three-dimensional modeling and finite element analysis. By comparing with the technical indexes of foreign similar products, the data and the environmental adaptability are verified. The study has advantages in performance, structure and cost, and has broad application prospects.

This paper investigates the fabrication process and performance characteristics of graphene-based flexible temperature sensors. The working mechanism of graphene flexible temperature sensors is first elaborated, followed by an exploration of the sensor unit fabrication method using polydimethylsiloxane as the substrate material and graphene as the conductive medium. Through optimization of graphene paste formulation and screen printing technology, flexible temperature sensing units were successfully fabricated. Subsequently, systematic performance tests were conducted on the sensing units, including resistance-temperature characteristic analysis and temperature cycling stability evaluation. Experimental results demon-strate that the fabricated sensing units exhibit excellent performance in terms of resistance-temperature characteristics and cycling stability, showing potential for industrial-grade applications. This study provides important technical support for the practical application of graphene flexible temperature sensors.

A subdivision stepper motor driver is designed based on ARM processor MM32SPIN0280. The main features include external MOS transistor driver, half-bridge driving circuit and current acquisi-tion circuit, which realizes current loop control of motor. The attenuation mode, current sampling time and constant torque vector control method of stepper motor are analyzed in detail. The functions of bootstrap circuit and driving resistor are expounded and quantitatively calculated, which provides theoretical basis for practical circuit design. The design of PWM output and sampling time and the realization method of constant torque vector control are discussed for software. Through the actual motor coil current measure-ment, the advantages of high subdivision drive for constant torque and small current fluctuation are demon-strated. By comparing the current waveforms in the case of 16 and 2 subdivisions, it is proved that the motor torque is more stable and the noise is less when running in high subdivision. The design provides a valuable reference for the development of miniaturized and high-performance stepper motor drivers.

In order to reduce the influence of uneven brightness and dark image and large gray difference between bleeding spots on the detection results of retinal bleeding spots, a retinal bleeding spot detection algorithm based on zero threshold of gray amplitude histogram and regional feature analysis is proposed. The algorithm realizes the shadow correction of the image through the large-scale median filter, and suppresses the background interference points by combining the concave-convex line segments to complete the pre-processing operation. Automatic threshold segmentation of dark targets is carried out by the first zero point in the amplitude histogram of each row and column, and the continuity of blood vessels is improved based on the region growth of amplitude characteristics. According to the different shapes between blood vessels and bleeding points, blood vessels are removed, and bleeding points are segmented. The test results in DIARETDB1 public gallery verify the effectiveness of the algorithm.

To meet the low-noise and low-offset requirements of analog front-end detection circuits, a programmable gain amplifier based on chopper stabilization technique fabricated using 0.18 μm CMOS process is introduced. The chopper stabilization technique is employed to reduce offset and low-frequency 1/f noise, while the programmable gain stage is used to improve the utilization of the analog front-end cir-cuit's output swing, meeting detection needs in various environments. The amplifier's equivalent input noise integral value from 1 Hz to 10 kHz is 1.43 μV, and it achieves an op-amp input impedance of 4.52 GΩ using an impedance enhancement circuit. A C-2C capacitor array is adopted as a variable capacitor array, enabling gain adjustment from 0 to 15 times with a minimum step of 1/64, which has wide application scenarios for low-noise circuits requiring fine-tuned gain adjustment.

This paper investigates the electro-thermal coupling topology optimization based on the SIMP density method. First, a SIMP density model was established, and the physical relationships and optimization objectives in the electro-thermal coupling system were analyzed. During model establishment, key parameters such as material thermal conductivity, electrical conductivity, and convective heat transfer coefficient were considered, and the concept of adaptive filter radius was introduced. The research shows that the choice of density model, the generation and distribution of Joule heat, and the setting of objective functions significantly affect the optimization results. By comparing structures optimized with different filter radii(0.2 mm, 0.4 mm, and 0.8 mm), the effects of various parameters on temperature distribution and structural performance were analyzed. The experimental results demonstrate that appropriate filter radius selection can effectively improve structural performance and reduce temperature standard deviation. This study provides theoretical foundation and practical guidance for the design optimization of electro-thermal coupling systems.

This study aims to enhance the user experience of voice communication systems by addressing issues in traditional adaptive filtering algorithms, such as nonlinear echo residual, noise suppression, and degraded speech quality in double-talk scenarios. A joint echo and noise cancellation algorithm based on a deep bidirectional gated recurrent unit network is proposed. The algorithm extracts speech sequence features through a fully connected network, trains the model with the ideal ratio mask(IRM) as the target, and reconstructs speech by combining phase information. The RMAE of a fused loss function is employed to improve model robustness. Experimental results demonstrate that the algorithm significantly enhances speech quality and intelligibility in double-talk, nonlinear echo, and noisy environments, outperforming traditional and other deep learning methods.

The study aims to optimize PID parameter control using self-tuning fuzzy control technology, addressing issues such as complex parameter adjustment and insufficient precision in traditional PID control. By employing fuzzy control rules with error(e) and error change(ec) as inputs, self-tuning of parameters is achieved. The self-tuning fuzzy PID controller is successfully simulated using the Simulink module in MATLAB, and its implementation method in MATLAB is demonstrated. Results show that the controller exhibits fast response, high-precision adjustment, and excellent stability, with no overshoot or oscillation. The research provides an efficient and stable solution for control system design, demonstrating significant practical application value.

To address the issue of rain streaks remaining due to the poor extraction of rain line features by existing image deraining algorithms, an image deraining network based on dense hybrid attention and global compensation is proposed. Shallow features of the input rainy image are extracted through multi-layer convolution operations. By integrating the advantages of dense connections and residual networks, a dense residual attention module is designed by introducing multiple attention mechanisms to achieve feature recycling and capture multi-scale features of the image. A global compensation module is added to ensure the comprehensiveness of feature extraction. Features are reconstructed through convolutional layers to obtain a clear and rain-free image. Experimental results show that the proposed algorithm outperforms existing classical and novel algorithms, effectively removing rain streaks and enhancing the overall visual quality of the image.

To address the challenge of detecting low-frequency and randomized covert attacks in com-munication networks and the inefficiency of existing methods, this paper designs a detection algorithm for large-scale data flow covert attacks. The algorithm avoids iterative processes by mining energy consumption features and calculating parameter variation coefficients, constructing a lightweight detection model with optimized packet forwarding monitoring mechanism. Experimental results show that the algorithm can detect covert attacks within 1 second, restore communication signals within 3 seconds, and achieve over 93% scalability. The research provides a new technical solution for enhancing communication network security and demonstrates good application value.

To address the issue of low power efficiency in charge pumps, a four-stage two-branch charge pump boost circuit with charge recycling structure is designed. The charge recycling switches con- nect voltage plates of boost capacitors at different potentials to achieve charge recovery, improving power efficiency. A cross-coupled voltage boosting circuit provides control signals for high-voltage charge transfer switches, simplifying the circuit structure. Three-phase non-overlapping clocks separately control the high-voltage clock generation circuit and charge recycling switches, preventing charge leakage at nodes during potential changes. Simulation results show that the circuit can output 20.11 V under a 5 V power supply. The maximum power efficiency reaches 44.35% and 51.33% before and after enabling the charge recycling function respectively.

With the development of modern emergency fire-fighting towards intelligence, multi-func-tionality, and miniaturization, wearable devices need to meet both comfort and lightweight requirements to address uncertainties and diverse scenarios in emergencies. Taking the smart infrared AR firefighting mask as an example, this paper elaborates on its design and implementation methods, and analyzes the pain points in emergency firefighting processes. The paper focuses on the application of key technologies such as flexi-ble electronics, micro-nano integration, multi-modal network communication, and artificial intelligence in wearable firefighting equipment. Research shows that the integrated application of these new technologies can significantly improve the intelligence level and practical performance of firefighting equipment. The research findings provide technical support and innovative ideas for the development of smart emergency firefighting wearable devices.

Repeated positioning accuracy is an important performance index of some moving object，which is relatively simple measuring method is to use a ruler or tape measure to measure directly and manually，which is difficult to ensure measurement accuracy，and the measurement efficiency is lower，the consistency of multiple measurements is not good，but the cost is lower。Another measurement method is to use an expensive coordinate measuring instrument，the accuracy of this measurement method is very high，and the consistency of repeated measurement is good，but the cost is very high。According to the advantages and disadvantages of the above two measurement methods，the motion model of the object is establish at first，then the mathematical model which is easy to understand and realize is abstracted from the motion model，finally，based on the mathematical model，by means of electronic technology，the displacement laser sensor is selected as the measurement distance means，and the repeated positioning accuracy detection system is designed。This system is simple to operate and the measurement accuracy is higher and has a low cost。

To enhance the logic density of individual transistors and reduce the number of transistors required for XNOR logic implementation, a novel XNOR logic gate based on a Schottky barrier resettable field-effect transistor is study proposed. The device uses NiSi as the metallic compound for both source and drain terminals, forming similar Schottky barriers between the source/drain electrodes and silicon's conduction and valence bands. Analysis and verification are conducted using Silvaco TCAD software to study the device's transfer characteristics, energy band variations, and carrier concentration distributions under different gate voltages. Results show that this design improves forward conduction current and achieves XNOR logic functionality using only one transistor, increasing semiconductor chip integration density compared to traditional CMOS technology, which has significant technical value for integrated circuit development.

To address the problems of short-channel effects and increased leakage current caused by device size scaling , a Complementary Schottky Barrier Source Reconfigurable Field-Effect Transistor(CSBS-RFET) is proposed. The reconfigurable output current, energy band, and carrier concentration distribution under different gate voltages are investigated and verified through Silvaco TCAD simulation. Experimental results show that the design using undoped semiconductor forming low Schottky barriers with Er and Pt metals can effectively enhance the forward conduction current while significantly reducing the off-state current and power consumption. This device shows promising application prospects in the field of high-speed information processing chips.