Accurate quantitative risk assessment is critical for decision-making in fields such as finance and healthcare. However， traditional methods fail to capture the complex nonlinear relationships among risk factors. This study proposes a novel risk quantification model integrating causal inference and graph neural networks （GNNs）. The model constructs a risk event graph， extracts features using graph convolutional networks （GCNs） and graph attention networks （GATs）， and captures risk propagation mechanisms. The core innovation lies in the introduction of causal inference methods， which can not only predict risks but also reveal causal relationships between risk factors， greatly improving the interpretability and reliability of the model. After training and optimization， the model can quantitatively assess new risk events and output risk indicators and volatility forecasts. Causal inference further improves the model’s transparency and assists decision-makers in understanding assessment logic and causal mechanisms. Experiments verify that the proposed model achieves outstanding performance in multiple risk assessment scenarios， can effectively process unstructured data， and exhibits significant advantages in improving assessment accuracy and interpretability.

Event evolution in the real world exhibits adaptive characteristics influenced by multiple factors， making the ranking of key nodes particularly challenging. To address this scenario， a network node importance ranking model （ICUPN） integrating public opinion event types and cascade position information is proposed. This model utilizes user preference tendencies within graph networks， employing a divergence-based semi-supervised graph convolutional network label propagation algorithm to identify node categories. Simultaneously， it integrates cascade sequence information into node features via cascade position encoding technology. Subsequently， a dual optimization strategy combining regression loss and listwise ranking loss refines model performance to achieve precise ranking of critical nodes. ICUPN employs an attention mechanism to adaptively learn the evolution patterns of public opinion events on graph networks. Evaluations on douban and weibo datasets show NDCG correlations for node ranking exceeding 97% and 93%， respectively， validating the model's high efficiency in addressing the critical node ranking problem within adaptive public opinion event evolution patterns.

Low-frequency signals， particularly those below 20 MHz， are often subject to the engineering misconception that signal integrity （SI） considerations are unnecessary. This paper presents a practical case study involving a 7 MHz clock frequency SPI interface， where communication failures occurred during sensor data acquisition. Through Fault Tree Analysis （FTA） and a series of comparative experiments， the underlying failure mechanisms were thoroughly investigated. The results indicate that the root cause of the failure stems from multiple impedance discontinuities within the "driver-transmission line-receiver" link. These discontinuities， combined with an excessively high driver slew rate setting and subtle variations in device distributed parameters and transmission line process parameters across temperature extremes， collectively led to severe signal integrity degradation. Based on these findings， targeted design improvement recommendations are proposed， offering practical guidance for the reliability design of low-frequency buses. This case study serves as a critical reminder that a low operating frequency does not equate to zero risk， urging engineers to abandon this fallacy and enhance the reliability of engineering designs.

In the production process of a microcontroller， in order to avoid metal surface oxidation during the post-plating test and screening test after the completion of plastic sealing， the microcontroller circuit is tinned on the side of the pin， that is， secondary plating. The effects of secondary electroplating on microcontrollers were analyzed through group tests. The results showed that occasional delamination occurred after secondary electroplating. However， delamination deteriorated further during the screening of high-temperature daily cycle test and temperature shock test， and water vapor was absorbed in the delamination space. Under the action of temperature， due to the difference in the expansion coefficient between the plastic sealing materials and the internal water vapor expansion， the stress is applied to the metal wires of the microcontroller circuit and the ground， so that the metal wires and the isolation layer between the metal wires are damaged， and finally the voltage of the circuit VDD port is abnormal and the microcontroller fails.

This article provides a systematic review of the innovative applications of graphene heating films in modern agriculture as well as their key preparation technologies. Regarding fabrication techniques， the paper critically examines the technical routes and applicability of physical methods （mechanical exfoliation， liquid-phase exfoliation）， chemical methods （oxidation-reduction method， chemical vapor deposition）， and printing methods （screen printing， inkjet printing， gravure printing）， highlighting the importance of tailoring process selection to specific application scenarios. At the application level， graphene films demonstrate considerable potential across multiple agricultural domains： in crop production， their lightweight nature and superior thermal management capabilities enable precise temperature control and energy savings in greenhouses， with field tests showing promising results in overcoming challenges such as frost protection for fruit trees and weed management； in livestock breeding， their energy-efficient and uniformly heated insulation systems significantly enhance the care of young animals and improve the environmental conditions of livestock housing； in occupational safety， smart wearable film devices contribute to increased comfort and safety for agricultural workers. Looking ahead， further advancements in graphene films must address key technical challenges， including cost reduction， industrial standardization， and performance stability under complex operational conditions. With continued technological integration and innovation， graphene heating films are poised to play a pivotal role in accelerating the transition toward intelligent and sustainable agricultural systems.

Node importance in graph structures is typically measured by centrality metrics. Traditional centrality definitions， primarily based on shortest-path or random-walk models， inadequately account for the dynamic characteristics of actual propagation processes， leading to limitations in application scenarios such as information diffusion optimization and propagation control. Building upon the epidemiological Susceptible-Infected-Recovered （SIR） model， a novel node centrality metric termed Spreading Centrality （SC） is proposed， along with an efficient algorithm for its computation. This metric effectively captures the criticality of nodes within graph networks. The designed algorithm efficiently computes the Spreading Centrality for all nodes in a graph by constructing a single-source directed complete graph and employing reverse computation， effectively enhancing the identification of key nodes in event evolution scenarios. Systematic validation was conducted on standard graph network datasets of varying scales， establishing a node importance ranking system based on SC values. Finally， comparative experiments with classical centrality metrics confirm the significant advantage of the SC metric in identifying critical network nodes， with its performance improvement remaining consistent across test networks of diverse topological structures.

This work proposes and validates a single-device XNOR logic gate （SDUT-RSD） based on a source/drain undoped tunneling Schottky diode structure. The device innovatively employs symmetric Schottky barriers formed by the contact between Ni and intrinsic silicon， thereby eliminating the need for an additional control electrode. The XNOR logic functionality is realized solely through the cooperation of a programmable gate and the drain terminal. Compared with conventional CMOS implementations that can achieve reconfigurable logic， the proposed device effectively enhances logic density. The transport characteristics， band modulation and carrier distribution of the device are systematically analyzed and verified using Silvaco TCAD simulations. The results show that the device as a switching element achieves higher sensitivity. The undoped structure can regulate the conduction type with a lower gate voltage while reducing power consumption， providing a feasible path for the development of low-power and high-density integrated circuits.

In the design process of FPGA， it is of great significance to reduce the cost and improve the reliability of the product by performing failure analysis to improve its production yield. However， it is difficult to accurately locate circuit failure nodes in very large-scale complex structures. In this paper， an efficient and convenient method for locating failure nodes of interconnect circuits is proposedfor locating failure nodes of interconnect circuits is proposed， which takes advantage of the repeatable programming and flexible construction of the FPGA. The software repeatedly and automatically layouts and routes the large series of inverter chain to debug the upper board， and constantly detects the signal states of the intermediate circuit nodes， thereby gradually locating the failure nodes of the interconnect circuit. Compared with traditional ATE testing， the method proposed in this paper can more accurately locate circuit defects and improve the efficiency of failure analysis. This method has guiding and reference significance for the process of FPGA testing and failure analysis.

This paper proposes a test vector generation method based on JTAG timing simulation， aiming to enhance the efficiency of integrated circuit testing. Through an in-depth analysis of the standard timing specifications of the JTAG protocol， an accurate timing model was established， and a corresponding vector generation algorithm was designed. Taking the electrical parameter testing of the C8051F005 circuit as an example， this method can effectively generate JTAG-compliant test vectors. These vectors are applicable in the J750HD integrated circuit test system， enabling the completion of corresponding parameter tests and achieving the expected results. This study addresses the issues of cumbersome manual configuration， difficulty in maintenance， and scalability in traditional JTAG vector generation methods. By employing timing modeling and automated generation algorithms， it provides an efficient and reliable solution for integrated circuit testing， enhancing testing efficiency by over 50% and demonstrating significant engineering application value.This study provides an efficient and reliable solution for integrated circuit testing， demonstrating significant engineering application value.

As the resolution and sampling rate continue to increase， low-power successive approximation register analog-to-digital converters （SAR ADCs） face new challenges in energy efficiency optimization， mismatch error suppression， and parasitic effect control. Meanwhile， owing to their excellent trade-off among accuracy， speed， and power consumption， SAR ADCs have become the preferred architecture for low-power， compact electronic devices such as wearable medical equipment and Internet of Things nodes. The internal capacitive digital-to-analog converter （CDAC） not only determines the conversion linearity but also serves as the primary source of dynamic power consumption， and different switching strategies have a significant impact on power consumption. This paper reviews recent advances in CDAC switching strategies and provides a detailed analysis of various methods， including conventional capacitor switching， charge sharing， monotonic， VCM-Based， bypass-window， and merged-capacitor approaches， thereby offering valuable references for the design of low-power SAR ADC.

This paper addresses the challenge of profile control in shallow trench isolation etching for integrated circuit manufacturing process. Based on inductively coupled plasma etching equipment， the effects of process parameters such as pressure， bias voltage， oxygen flow rate， HBr：Cl₂ flow ratio and mask clear ratio on the side wall angle， trench bottom topography， critical dimensions， and uniformity were systematically studied. Through experimental design and process optimization， combined with the mechanism of plasma etching， the coupling mechanism among various parameters was revealed， and a profile control process window for mass production was established， providing theoretical and practical references for the optimization of shallow trench etching processes in integrated circuit manufacturing.

Given that the moisture content at the exit of the cut tobacco drying process is a core indicator affecting the quality of tobacco shreds and the stability of subsequent processing in cigarette production， to reduce the complexity of data in the cut tobacco drying process， improve the accuracy of the moisture content prediction model at the outlet， and optimize the cost of sensor deployment， a multi-source feature selection method for the moisture content at the exit of the cut tobacco drying process based on the maximum relevance-minimum redundancy （mRMR） algorithm is proposed. Taking the monitoring data of a cut tobacco drying production line in a certain cigarette factory as the research object， through processing and analyzing the multi-source feature data of three categories： material characteristics， process parameters， and equipment status， the mRMR algorithm is used to screen out key features with high relevance and low redundancy. The experimental results show that this method can effectively identify the core factors affecting the moisture content at the exit of the cut tobacco drying process （such as hot air temperature， initial moisture content of tobacco shreds， etc.）， reduce the number of sensor deployments by more than 40%， at the same time， the prediction accuracy has increased by 35.01%，providing a scientific basis for precise control and cost optimization of the cut tobacco drying process.

This paper systematically presents a multi-device SPI communication design featuring Cyclic Redundancy Check （CRC） capability. The single-master multi-slave communication mechanism holds promising application prospects in multi-device environments such as smart homes and industrial control systems. However， traditional slave selection methods are constrained by the limited number of available I/O ports， and the selection approach is relatively inflexible. To address this issue， this paper proposes a multi-device communication circuit designed to resolve the slave selection problem in multi-device communication scenarios. The method is briefly summarized as follows： the master device initiates communication and selects the target slave device through an address select line （AD）； all non-target slave devices are prevented from processing the received information. Additionally， a CRC algorithm module is integrated into the conventional SPI communication framework， enabling effective detection of transmission errors caused by noise and other interference， thereby improving data transmission quality， accuracy， and reliability. The proposed design offers insights for multi-device communication management in related industries， with advantages including reduced I/O resource consumption and enhanced communication quality. This paper comprehensively describes the design philosophy of each functional module， and the fundamental hardware circuit design is validated through simulation， confirming the rationality of the design.

High precision pressure and temperature acquisition systems have wide applications in underwater detection equipment， instruments， aerospace equipment， and weapon equipment， but they face problems such as low sampling accuracy and high device power consumption. The STM32F103C8 microcontroller is selected as the main control unit， and the compact ADS1220 with low noise and low power consumption integrated with PGA is used as the analog-to-digital converter. The four-wire resistance bridge pressure sensor is used for pressure signal conversion， and the three-wire RTD is used for temperature signal conversion. The digital filter is used for effective harmonic suppression. The collected data are processed by software algorithms to reduce ADC noise and aliasing， improve the measurement range and accuracy of pressure and temperature acquisition， and study the high-precision pressure and temperature acquisition system. On the premise of ensuring the reliability of the system， the power consumption of the system can be further reduced by making the microcontroller and ADC into sleep mode when data collection is not required.

Risk is defined as the probability of harmful consequences or expected losses resulting from the complex interaction between hazards and vulnerabilities in urban and social contexts. In view of the problems of indicator information redundancy， difficulty in indicator coupling and parsing， and semantic ambiguity existing in the current methods， this study proposes a mask-based risk prediction model based on Multi- hierarchical Graph Attention Network （MMHGAT）， which realizes thetrategy and graph attention mechanism. The model adopts the multi-level graph structure modeling method and combines the cross-level attention learning mechanism to effectively capture the complex correlation between multi- level indicators. Experimental results show that compared with the traditional graph neural network method， the mean square error （MSE） of MMHGAT is reduced by 10.1% in the risk assessment task. The MSE is 20.7% lower than that without masking. This achievement provides a new technical idea for the field of risk prediction， and has application value in many fields such as emergency management and financial risk control.

To address the problems of blind spots in traditional fixed surveillance， low efficiency of manual inspection， and high maintenance costs， this paper designs an automated monitoring robot. A monocular camera is used for image acquisition and surveillance， as well as for color guidance and target tracking. A LiDAR sensor is employed to acquire environmental data， and a mapping algorithm is used to construct the map and estimate the robot’s poses. Based on a path planning algorithm， the robot achieves autonomous navigation and obstacle avoidance. The core contribution of this paper is not the proposal of a completely new theoretical algorithm， but rather the integration at the system level： a low‑cost infrared imaging module is combined with visible light vision and LiDAR SLAM into a unified indoor monitoring robot system. To meet the monitoring requirements in low‑illuminance environments， an infrared array sensor together with an infrared data imaging algorithm is adopted to realize infrared imaging of the monitored area， thereby solving the problem that conventional visible‑light cameras fail in dark environments. This work is of great significance for the automated and intelligent management of indoor equipment.

Aiming at the problems of lack of flexibility in data acquisition and lack of integrity in data transmission of the RS422 bus in airborne equipment， a RS422 bus data acquisition and transmission system based on FPGA and connected to the upper computer through the Ethernet interface is designed and developed. This system enables flexible configuration of various parameters and complete data transmission. The design implements flexible configuration of arbitrary baud rate and other parameters based on the RS422 bus for data reception.Meanwhile， according to user requirements， it can collect all or part of the received data and achieve complete data transmission through packet disassembly. The functions of data reception， data acquisition and data transmission are verified at the board level through on-site parameter configuration by the upper computer software. The results show that all the above functions can be realized.