Fiber-optic acoustic sensors are a novel type of acoustic detector based on optical principles. They offer excellent characteristics such as immunity to electromagnetic interference， compact size， and high sensitivity， making them widely applicable in fields including marine exploration， industrial non-destructive testing， and medical diagnostics. Depending on the signal modulation mechanism， fiber-optic acoustic sensors are primarily classified into intensity-modulated， phase-modulated， and fiber Bragg grating types. Intensity-modulated sensors are affected by the structural properties of the optical fiber itself， leading to limitations such as relatively low sensitivity， narrow dynamic range， and susceptibility to environmental interference. In contrast， phase-modulated sensors exhibit high detection sensitivity and broad frequency response. Particularly， the Fabry-Pérot interferometric （FPI） type demonstrates a minimum detectable sound pressure of 0.28 μPa/Hz^1/2. Due to restrictions in the spectral sideband， fiber Bragg grating sensors show comparatively lower sensitivity， though they offer high structural stability and are suitable for harsh environments such as high temperatures and high pressures. Currently， all types of fiber-optic acoustic sensors are continuously advancing toward miniaturization， higher sensitivity， and improved acoustic coupling efficiency， demonstrating broad application prospects.

This study presents an FPGA-based test system for ultra-high-speed ADC chips. It focuses on the design principles of the system， including the clock tree network of the test system and the power network design of the data acquisition system. The system implements an acquisition platform based on FPGA for data collection and caching of ultra-high-speed ADCs， as well as a dynamic performance test software system. It also provides an adjustable， ultra-high-precision， low-jitter clock signal. Results show that the ADC chip achieves an SNR of 34.03 dBFS and an ENOB of 5.65 bits at 1 GHz， and an SNR of 30.07 dBFS and an ENOB of 4.58 bits at 20 GHz. The test results are consistent with the chip datasheet， indicating that the test system meets the requirements for ultra-high-speed ADC testing and can also be applied to 8-bit or 12-bit ADC chips with sampling rates above 12 Gsps.

To improve the privacy and security of medical images， a joint algorithm integrating YOLO image recognition and chaotic system-based image encryption is proposed. First， the optimal recognition model is determined through comparative experiments on multiple versions of the YOLO model. Then， simulation experiments are conducted on the proposed encryption algorithm and the recognized images to generate encrypted images. The feasibility of the algorithm is verified by encrypting the recognized target images. Meanwhile， common images are selected for encryption processing and compared with other encryption algorithms. The performance of the algorithm is verified by combining methods such as histogram test， correlation test， NPCR and UACI tests. The results show that the proposed algorithm can effectively realize the coordinated operation of medical image recognition and encryption， and has high privacy protection security and reliability.

With the rapid development of integrated circuits， low-power system-on-chip （SoC） design methodologies are increasingly favored by engineers. Low-power SoC design approaches can be categorized into three tiers： architecture-level， logic-level， and physical-level. These encompass various aspects such as multiple operational modes， configurable peripherals， manual logic optimization， clock gating， logic and power optimization using electronic design automation （EDA） tools， clock tree design， multi-threshold library selection， power gating， multi-voltage operation， multi-voltage domain implementation， and backup domain design. This serves as valuable technical reference for design engineers.

To meet the demand for pressure monitoring in high-temperature environments， this study designs and demonstrates an all-SiC piezoresistive pressure sensor based on a 4H-SiC epitaxial layer. A parameterized finite-element model is established in COMSOL to compare the stress and deflection responses of circular and square diaphragms under 0-3 MPa loading， leading to the selection of the circular-diaphragm design. Electro-thermo-mechanical coupled simulations are further conducted to evaluate the output characteristics over a wide temperature range of 0-500 ℃. A hybrid diaphragm fabrication process combining femtosecond-laser pre-machining with ICP etching is proposed to enable efficient thinning of the thick substrate while improving surface quality. The test results show that the sensor exhibits a good linear output in the range of 0-3 MPa， with a full-scale output of 44.554 mV， a normalized sensitivity of about 1.49 mV/（V·MPa）， a maximum deviation of 4.19% from the linear fitting curve， and a hysteresis error as low as 0.0045%FSO. These results indicate that the proposed structural design and composite fabrication process can meet the requirements of high-temperature pressure measurement and provide a reference for the design and fabrication of all-SiC high-temperature pressure sensors.

Over the past decade， the rapid development of artificial intelligence， photovoltaic technology， home appliances， and automotive industries in China has significantly driven the growth of chip demand， while also imposing more stringent requirements on chip performance. Particularly in high-voltage operating environments， some chip pins need to transmit signals exceeding the power supply voltage. To address this need， a high-voltage-tolerant electrostatic discharge （ESD） protection circuit is designed. This circuit adopts an innovative dual-gate grounded NMOS （dual-GGNMOS） architecture. The test results showed that the design meets ESD testing standards and provides effective electrostatic protection for high-voltage input pins.

A gate-all-around （GAA） based highly integrated single-device inverter is proposed to address the limitations of Moore's Law in traditional field-effect transistor inverters. The device employs an asymmetric bias architecture （with the source connected to V_SS for low voltage and the drain connected to V_DD for high voltage）， constructing a high Schottky barrier at the conduction band interface between the source and the central silicon region. Carrier transport is achieved through a direct tunneling mechanism （tunneling probability >85%）. Simultaneously， a low Schottky barrier is optimized at the drain-valance band heterojunction， effectively eliminating parasitic hole injection. The GAA structure enables the device to realize the fundamental functionality of an inverter using only a single transistor. Simulations conducted using Silvaco TCAD demonstrate that the design successfully achieves inverter functionality， offering higher integration density and lower power consumption compared to traditional CMOS inverters.

Aiming at the limitations of bidirectional applications in reconfigurable field-effect transistors （RFETs） with double-gate structures and complementary source-drain doping， as well as the operational complexity arising from the simultaneous power supply requirement for both the control gate and program gate， a bidirectional highly integrated reconfigurable field-effect transistor with a triple-gate and floating-gate structure and complementary source-drain doping is proposed. The triple-gate structure of the device optimizes symmetry in bidirectional applications. During fabrication， the triple-gate structure eliminates the stringent self-alignment concerns associated with the formation of the control gate in double-gate designs. The floating program gate enables single-gate powered operation， while the non-volatile charge storage characteristic of the floating gate effectively reduces static power consumption. In terms of integration density， the device adopts a U-shaped design to enhance compactness.

To meet the demands of modern communication systems for high-frequency signals and high precision， a high-stability on-chip RC relaxation oscillator is designed based on TSMC 180 nm technology， building upon the traditional RC oscillator structure to provide a stable clock signal for the chip. The voltage-averaging feedback technique is adopted to mitigate the impact of comparator delay. A reference circuit ensures high frequency stability across a wide supply voltage and temperature range， while a digital trimming circuit enhances precision. The results showed that under a 4 V supply voltage， at 25 °C， and in the TT process corner， the output frequency was 2.004 MHz with a 50% duty cycle and an accuracy of +0.2%. Simulations across TT， FF， and SS process corners under varying temperatures and supply voltages demonstrated maximum frequency deviations of 0.416% and 0.315%， respectively.

To support the development of the national standard for Chiplet interconnect interfaces and conduct technical validation， this study focuses on verifying the physical layer architecture design of the Chiplet interconnect based on the hierarchical die-to-die （D2D） interface transmission protocol proposed in the national standard "Specification for Chiplet Interconnect Interface （Draft）." The research employs Verilog hardware description language to develop a behavioral-level model of the physical layer for the Chiplet interconnect protocol and completes simulation and verification. The study concentrates on the data processing mechanisms of the transmitter （TX） and receiver （RX）， analyzing the implementation principles and performance of both NRZ and PAM3 encoding schemes. Through waveform simulation experiments， the timing alignment characteristics of TX and RX under NRZ and PAM3 modes are validated， ensuring the accuracy and reliability of data transmission. Additionally， the serial-to-parallel conversion logic of TX and the multi-level decision mechanism of RX are implemented. Finally， the physical layer architecture design is synthesized using Vivado. The results demonstrate that the proposed behavioral model of the physical layer effectively supports the functional requirements of the Chiplet interconnect protocol， with a 11% reduction in latency and a 33% reduction in power consumption. This study provides an experimental basis for the design and optimization of high-performance Chiplet interconnect architectures and offers valuable insights for research and engineering applications in related fields.

To achieve the goal of time-domain discretization under low-power conditions， this study systematically compares and analyzes various technical schemes， including Flash-type ADC architecture and pipeline-type ADC architecture. Breaking through traditional design paradigms， it innovatively introduces a ring oscillator as the core module to construct a time-domain discretization functional unit with high energy efficiency. Based on the mathematical modeling framework of the voltage-controlled oscillator （VCO）， this study systematically demonstrates the feasibility of physical implementation of phase-domain discretization technology and uses the Matlab and Simulink co-simulation platform to build a system-level simulation model covering both ideal and non-ideal conditions， verifying the correctness of theoretical derivations through multi-scenario simulations. Based on the modeling and analysis framework built on the Simulink simulation platform and supported by TSMC 65 nm CMOS technology， this study completes the transistor-level full-circuit integrated design， constructs a complete system architecture of a continuous-time Sigma-Delta analog-to-digital converter based on the VCO core module， and successfully implements a pre-layout simulation verification process with fourth-order 4-bit quantization accuracy. The simulation analysis results showed that under the system configuration of 256 MHz sampling frequency， 1.2 V power supply voltage， 8 MHz signal effective bandwidth， and 16 times oversampling ratio （OSR）， using Spectre and FFT spectrum analysis techniques to comprehensively verify the system performance， the system signal-to-noise and distortion ratio （SNDR） and effective number of bits （ENOB） both met the design requirements.

Aiming at electronic systems susceptible to single-event latch-up effects in space applications， an overcurrent protection module with automatic reconnection capability is designed. This module can be installed between the power supply and the single-event latch-up-sensitive system load. When the system load draws excessive current due to single-event latch-up， the module can play the function of overcurrent protection， cutting off the power supply of the system load， allowing it to recover from the latch-up state. Subsequently， the automatic reconnection function enables the system load to automatically restore power and resume operation. When the overcurrent threshold was set below 260 mA， the error accuracy was controlled within ±18%； when the threshold range was set between 600~1 000 mA， the error accuracy was controlled within ±10%. The automatic reconnection time can be adjusted as required. The module is fabricated using layered stacking and epoxy resin potting technology， with electrical connections between internal substrate layers achieved through metal plating on the module’s sides. The overall dimensions of the module are 15 mm × 15 mm × 12 mm， and it weighs less than 8 g.

In response to issues such as insufficient depth， low efficiency， and limited value in data analysis within university informatization systems， this study proposes an artificial intelligence-based educational data analysis method. The approach employs deep learning techniques and follows a processing paradigm of "feature extraction-pattern recognition-predictive analysis" to achieve intelligent analysis of educational data. It utilizes a multi-stream autoencoder for feature extraction of heterogeneous data， an improved Transformer architecture for educational pattern recognition， and a multi-task learning framework for predictive analysis. The results demonstrate that compared to traditional methods， this approach achieved significant improvements in feature representation， pattern recognition， and predictive analysis， providing an effective solution for the application of artificial intelligence technology in analyzing educational data in university teaching.

High speed wideband differential operational amplifiers are widely used to drive high speed and high precision ADCs， and their performance directly affects the quality of signal conversion between analog and digital systems. Generally， the supply voltage is as low as 1.8~3.3 V，which greatly limits their output range. This paper analyzes the working principle and characteristics of a high speed wideband differential operational amplifier capable of working at 5 V. The circuit contains high-speed transconductance units， common-emitter amplifier units and high-speed buffer units. The principles of its high speed broadband characteristics were analyzed and the circuit design， layout design， simulation design and tape-out were completed. The test results indicate that the operational amplifier has a supply current of less than 30 mA，a -3 dB bandwidth of more than 1 GHz and a slew rate of more than 1 000 V/μs at 5 V power supply conditions.

With the increasingly complex environment of modern radio communication systems， the need for covering more frequency bands， and the continuously rising demands for data processing capabilities， multi-channel synchronous acquisition systems are facing severe challenges. At the current stage， data acquisition systems struggle to meet the requirements for capturing high-frequency signals in terms of sampling rate， system bandwidth is insufficient for wide-spectrum signal transmission， storage capacity is inadequate for long-term continuous sampling， and the synchronization accuracy of multi-channels fails to meet the standards for precision measurement. To address the demand for multi-channel synchronous signal acquisition， a multi-channel synchronous acquisition system based on high-speed ADCs and field-programmable gate arrays （FPGA） has been designed. This system employs eight high-speed ADCs， utilizes time-interleaved sampling system mismatch error correction techniques， and achieves sampling of eight-channel signals operating at a rate of 5 GSPS. Each channel of the system features a data storage depth greater than 40 Mpts， a signal-to-noise ratio exceeding 48 dB， an effective number of bits greater than 7.7 bits， a spurious-free dynamic range exceeding 56 dBc， and synchronization accuracy better than ±100 ps. This design provides an effective solution for multi-channel synchronous signal acquisition.

To minimize the tunnel transistor size for higher integration density， an optimized structure of a novel high-low-high Schottky barrier bidirectional tunnel field-effect transistor （HLHSB-BTFET） based on the high-low-high Schottky barrier conduction mechanism is proposed and validated using Silvaco TCAD simulation software. The device abandons the conventional U-shaped gate structure in favor of a gate-all-around encapsulation， embedding the intermediate metal alloy internally to directly adjust the channel position. Its effective channel length is no longer directly determined by the distance between the source/drain and the intermediate metal but depends on the height of the insulating layer between the source and drain. This novel HLHSB-BTFET structure features a significantly reduced device size. Simulation results demonstrate that the optimized transistor exhibits almost no degradation in on-state current while achieving a substantial reduction in volume.

This study employs a fuse trimming circuit programming control method to design a low-dropout regulator （LDO） with fast transient response and high precision. The approach effectively corrects output voltage deviations in the reference module caused by offset factors， while an NMOS transistor is utilized as the pass device to enhance transient response speed. Simulation results demonstrated that the output voltage accuracy remained within ±1% under significant load and bias variations. Across different process conditions， the maximum line regulation was 0.000 353%/V. Within the load current range of 50~3 000 mA， the load regulation was 0.005 5%/A. When the load current increased from 50 mA to 3 000 mA at a slew rate of 1 A/μs， the undershoot voltage was 50 mV with a duration of 1.37 μs. Conversely， when the load current decreased from 3 000 mA to 100 mA at 1 A/μs， the overshoot voltage was 35 mV with a settling time of 2.8 μs. These results meet the design requirements for both high precision and fast transient response.

Recent advancements in visual-inertial measurement unit （IMU） fusion simultaneous localization and mapping （SLAM） technologies have shown substantial advantages in unmanned system localization. However， existing methods still face challenges in dynamically structured environments： limited feature extraction in low-texture scenes leads to decreased matching accuracy， while interference from dynamic objects causes feature mismatches， impacting localization precision. To address these issues， this paper proposes a visual-IMU fusion localization method for dynamically structured spaces. First， to mitigate the decline in feature matching accuracy in low-texture environments， an IMU-assisted point-line feature matching algorithm is introduced. By leveraging IMU pre-integration to predict feature positions and combining optical flow tracking， the method significantly improves matching success rates and reduces computational time. Second， to address mismatches caused by dynamic interference， a dynamic feature elimination strategy is proposed， integrating depth maps with object detection. This approach uses an edge-constrained depth completion algorithm to generate dense depth masks and incorporates a missed detection compensation mechanism to mitigate the effects of dynamic object mismatches. Experimental results show a 12.7% increase in feature matching success and a 68.3% reduction in dynamic feature mismatches in structured low-texture environments. This method is applicable to domains such as power systems.

This paper proposes an encryption algorithm based on two-dimensional chaotic system， aiming to meet the security and real-time requirements of image encryption. The algorithm adopts a double-round iterative framework， in which each round successively performs forward modular addition diffusion， dynamic DNA operation， Fisher-Yates shuffling， and reverse modular addition diffusion. An improved two-dimensional coupled Logistic-sine-cosine chaotic system is introduced to generate pseudo-random sequences， which are used to dynamically control the DNA coding rules， shift parameters， and shuffling indices， enhancing the algorithm's nonlinearity. The forward and reverse modular addition diffusion structures effectively improve the plaintext diffusion effect through the cumulative correlation between pixels. Theoretical analysis and simulation results show that the algorithm has strong key sensitivity， good resistance to differential attacks and statistical analysis， and can ensure high security， making it suitable for the confidential transmission and storage of digital images.

With the advent of the big data era， multimodal data has experienced explosive growth， and traditional unimodal semantic understanding methods face challenges such as large processing scales， semantic sparsity， and poor information complementarity. Multimodal fusion technology can effectively improve the accuracy and robustness of semantic understanding by integrating information from different perceptual channels. A hierarchical multimodal fusion application architecture is constructed， employing pre-trained models such as BERT and ResNet for feature extraction， designing cross-modal attention mechanisms for semantic alignment， and dynamically adjusting modal weights through gated fusion strategies. Under the support of distributed computing frameworks， optimization strategies such as intelligent sampling and incremental learning are applied to improve processing efficiency. Experimental results show that the proposed scheme performs excellently in scenarios such as e-commerce， social media， and news， achieving an F₁ score of 87.9%， which represents a significant improvement compared to baseline methods， validating the application value of multimodal fusion in big data semantic understanding.

This study proposes a nanoscale single XOR/XNOR device utilizing high-low Schottky barriers. Unlike conventional BRFETs， this device incorporates two distinct metal materials at the source/drain （S/D） contact interfaces with the silicon substrate， successfully constructing two types of Schottky barrier structures. The first metal forms a Schottky barrier height with the semiconductor conduction band that is less than half the bandgap width， while its Schottky barrier height with the valence band exceeds half the bandgap width. The second metal forms a Schottky barrier height with the valence band that is also less than half the bandgap width， while its Schottky barrier height with the conduction band is greater than half the bandgap width. As a result， the device forms a dual Schottky barrier with one high and one low （HLBSB）. Compared to traditional BRFETs， this device enables more carriers to enter the semiconductor region through thermionic emission in n-mode and p-mode， whereas conventional BRFETs primarily generate carriers through band-to-band tunneling. Consequently， the high-low Schottky barrier single XOR/XNOR device achieves a larger forward current. Through device simulation， the performance of the high Schottky barrier XOR/XNOR device is investigated and compared with that of BRFETs. Analysis based on energy band theory explains its operating mechanism， while its output characteristics are studied and validated.

With the rapid development of integrated circuit manufacturing processes， new challenges continue to emerge， as many fundamental device components increasingly fail to meet the high demands of modern IC design. In response to the limitations of conventional diodes in certain applications， researchers have proposed a novel Schottky barrier diode with resettable conduction types and non-volatile characteristics. This design utilizes a programming gate to inject charge into a floating gate， enabling the device to maintain its conduction type for extended periods even without power， thereby achieving low static power consumption and reduced reverse leakage current. This innovation not only enhances device efficiency but also offers new solutions for future IC design by improving integration density and reducing chip area.

A high-voltage rail-to-rail output digital-to-analog converter （DAC） is designed and implemented using a 0.18 μm 60 V BCD process. The circuit exhibits good monotonicity at a 12-bit resolution. A novel high-voltage rail-to-rail output operational amplifier based on a folded cascode structure is proposed. The first stage employs gain boosting technique， significantly improving the amplifier's speed and gain， while the second stage adopts a Class AB architecture to achieve rail-to-rail output operation. By flexibly configuring the output mode， users can freely select three output ranges： 40， 20， or 10 V. The DAC output stage is capable of driving ±30 mA current， effectively reducing the need for external operational amplifiers. Comprehensive simulation and verification of the DAC circuit are carried out. Results indicate that the integral nonlinearity （INL） and differential nonlinearity （DNL） are both below |0.3| LSB， and the settling time is within 1 μs. With a 1 MHz sinusoidal input signal， the signal-to-noise-and-distortion ratio （SNDR） reaches 72.54 dB， the total harmonic distortion （THD） is as low as -80.45 dB， and the effective number of bits （ENOB） reaches 11.76 bits.

The space environment contains high-energy particles， which pose a threat to normally functioning semiconductor devices. Compared with traditional bulk silicon technology， SOI technology isolates the active device substrate from the thin-film region using an oxide layer and a buried oxide layer， endowing it with advantages such as strong radiation resistance， high speed， and high reliability. However， due to the bird's beak effect generated by local oxidation of silicon isolation， SOI devices exhibit weaker resistance to total ionizing dose effects and still require reinforcement. Therefore， based on SOI technology， an H-shaped gate structure was designed at the layout level， while dual-interlocked storage cells（DICE） and C-cell were designed at the circuit level， thereby reducing the probability of chip failure in the space environment. Ground-based irradiation experiments using ion beams and a cobalt source were conducted on chips containing D flip-flops. When operating in scan chain mode， no single-event upsets or single-event latch-ups occurred， and the total ionizing dose resistance reached 100 krad （Si）.

Data flow processing applications impose higher requirements on the energy efficiency ratio of integrated circuits， while traditional fixed architectures struggle to adapt to diverse workload characteristics. A hierarchical heterogeneous energy-efficient adjustable architecture is proposed， which divides the system into four functional layers： computing layer， control layer， storage layer， and interconnect layer， and introduces 64 fine-grained power domains to achieve precise voltage and frequency regulation. Reconfigurable data flow processing units and distributed control mechanisms are designed， and adaptive working mode switching is realized through deep reinforcement learning algorithms. Simulation results show that compared with traditional architectures， power consumption is reduced by 32% and energy efficiency ratio is improved by 58%， validating the effectiveness of the architecture design.

The study proposes a bias circuit designed to stabilize the operating point of a low-voltage cascode current mirror. The advantage of this circuit lies in its ability to precisely set the drain-source voltage of the cascode transistor， thereby keeping the transistor operating within the designed region under process， voltage， and temperature （PVT） variations. Simulations based on a 0.18 μm CMOS process show that the current mirror maintains stable operation across a supply voltage range of 2.7 V to 5.5 V and a temperature range of -55 °C to 125 °C， while covering typical （tt）， fast （ff）， slow （ss）， and mixed （fs） process corners.

Hyperspectral images contain hundreds of spectral bands， each of which carries rich spectral information. Due to the significant differences in spectral responses of various ground objects across different bands， local features in the images are complex and diverse. Relying solely on single-feature point matching for deep segmentation limits the extracted features to sparsely distributed points， which may lead to the loss of critical local information and compromise the accuracy and completeness of the final segmentation results. To address this， this study proposes a deep segmentation method for hyperspectral images based on multi-feature point matching. The grayscale probability of the image is obtained to calculate the OTSU segmentation threshold. Within the set threshold range， the correlation between two pixels is analyzed， and multi-feature point matching is employed to comprehensively calibrate all feature points， ensuring a dense distribution of features. Nodes with high correlation are selected as matching targets for segmentation features， and fuzzy matching results are generated. These results are then imported into a constructed segmentation mapping matrix and converted into mapping feature nodes. With these nodes as the center， the image is progressively integrated and segmented， continuously expanding the segmentation range until the final deep segmentation objective is achieved. The results showed that the OA value of the segmented images remained stable above 80%， fully demonstrating the method’s significant advantage in improving segmentation accuracy.

Outlier detection in data stream environments is a significant issue in stream data management and analysis， with broad applications. Distance threshold-based methods determine whether an object in a window is an outlier. For any object o in the window， if the number of objects within a distance threshold r is fewer than the object count threshold k， then o is considered an outlier. Given the outlier detection parameters q<r，k>， q monitors the objects in the window. As the window slides， the algorithm returns the outliers within the window. Based on this， a novel index structure—GQDT—is proposed for efficient management of stream data. GQDT is a two-layer index structure， with the first layer being a grid index that probes the degree of data distribution， and the second layer consisting of a quadtree index. In regions with dense data distribution， GQDT further employs a quadtree for indexing to facilitate outlier detection. Compared to traditional grid and quadtree indexing methods， GQDT not only inherits the advantage of the grid index in quickly identifying certain outliers but also accelerates range queries for objects that cannot be directly determined， thereby returning all outliers.

Aluminum nitride （AlN） is a mature piezoelectric material， but its relatively low piezoelectric coefficient limits the further improvement of the performance of AlN-based filters. By combining AlN with hexagonal boron nitride （h-BN） with extremely high in-plane sound velocity， a "slow-fast system" can be formed， which can effectively excite Sezawa waves with high sound velocity and high electromechanical coupling coefficient. Therefore， a surface acoustic wave filter based on AlN/BN composite film is proposed. The device performance is analyzed by the finite element method， the influence of the thickness of the piezoelectric layer on the frequency domain characteristics of the device is studied， and the sound velocity and electromechanical coupling coefficient of the device are calculated. This structure has the characteristics of low insertion loss and high sound velocity， and shows good comprehensive performance， providing a feasible solution for the improvement of the performance of surface acoustic wave filters.

Zinc oxide （ZnO） is a conventional material for surface acoustic wave （SAW） devices， but its application in high-frequency devices is limited by its intrinsic acoustic velocity. In this study， sapphire was used as the substrate to design and comparatively investigate two SAW device structures， namely IDT/ZnO and IDT/ZnO/h-BN. The acoustic wave propagation characteristics of the devices， as well as the thickness matching relationship between ZnO and h-BN， were analyzed using the finite element method based on COMSOL multiphysics simulation. The results show that the introduction of an h-BN intermediate layer with ultrahigh in-plane acoustic velocity can effectively enhance the excitation of higher-order modes. The simulation results were further validated through device fabrication and experimental testing. These findings indicate that the ZnO/h-BN structure has promising potential for achieving high-frequency SAW devices.

This study proposes an XOR pass-gate transistor based on a gated diode. Due to the opposite polarity of the voltage applied between the gate and drain， tunneling occurs in the intrinsic silicon region between the two electrodes under a strong electric field. Meanwhile， variations in the drain voltage between the source and drain either form or lower a potential barrier， thereby controlling the turn-on or turn-off of the device's drain current. The surface potential and electric field are analyzed and modeled by solving the two-dimensional Poisson equation， and the tunneling current is calculated using the Kane model. Finally， the analytical results are compared and validated against Silvaco TCAD simulation results.

The Wide-area Multilateration System （WMPS） serves as core equipment in civil aviation air traffic management， and its network transmission performance directly affects the reliability and real-time performance of air traffic control （ATC） data. Aiming at the problem that remote stations in a certain local WMPS-I system abnormally receive broadcast data from other stations， posing a potential risk of network storms， a precision optimization configuration scheme based on Access Control List is proposed by combining the system's networking architecture and data transmission characteristics. Specific implementation steps and configuration examples are provided. Experimental verification shows that the optimization scheme can effectively block the transmission of invalid broadcast data， avoid the occurrence of network storms， and improve the stability of the system's network transmission. It holds significant practical significance for ensuring the safe operation of the civil aviation air traffic control system.

This paper addresses the challenge of profile control in shallow trench isolation etching for integrated circuit manufacturing process. Based on inductively coupled plasma etching equipment， the effects of process parameters such as pressure， bias voltage， oxygen flow rate， HBr：Cl₂ flow ratio and mask clear ratio on the side wall angle， trench bottom topography， critical dimensions， and uniformity were systematically studied. Through experimental design and process optimization， combined with the mechanism of plasma etching， the coupling mechanism among various parameters was revealed， and a profile control process window for mass production was established， providing theoretical and practical references for the optimization of shallow trench etching processes in integrated circuit manufacturing.

Under resource-constrained conditions， path selection must simultaneously meet the requirements of low latency， high reliability， and energy efficiency optimization. However， intrusion interference can compromise link stability， making static weight allocation unable to adapt to dynamic network states. This difficulty in flexibly adjusting routing strategies based on real-time intrusion conditions leads to increased false alarm rates， reduced detection accuracy， and impaired reliability in routing decisions. To address this， an optimized dynamic routing configuration method for computer networks that considers intrusion interference is proposed. This method establishes an intrusion interference model based on end-to-end routing probing and quantifies the impact of intrusions using topological feature parameters and detection coefficients. By defining a local time scale that integrates false alarm rates and detection rates， optimized selection of routing paths is achieved. Dynamic task allocation is realized through routing node evaluation， which assesses the transmission capability of nodes after interference and dynamically allocates bandwidth resources to ensure tasks are executed by efficient nodes. Multi-objective optimization is applied to configure wireless sensor network routing. An optimization objective function for routing configuration is defined and integrated into the network architecture. A genetic algorithm is employed to balance key metrics such as link cost， load， and energy efficiency， and a fitness threshold is introduced to select optimal cluster head nodes， thereby achieving multi-objective optimization for WSN routing and ensuring stable network operation in complex environments. The results show that this method maintains latency below 2 ms and keeps the packet transmission bit error rate under 0.1， effectively enhancing the reliability of data transmission in network routing.

To effectively reduce the error caused by the nonlinear temperature component of the bipolar transistor's emitter-base voltage， a high-precision， low-temperature-coefficient current-mode bandgap reference（BGR） circuit is designed using 65 nm CMOS technology. An enhanced segmented temperature compensation circuit is proposed. This circuit， triggered by different temperature thresholds， outputs compensation currents with different temperature coefficients across various temperature ranges， significantly reducing the impact of the nonlinear temperature component on the reference voltage. Cadence software is used for simulation verification. Under a supply voltage of 1.2 V and at room temperature， the circuit yielded a reference voltage of 800.5 mV， its relative error （3σ/μ） is as low as 0.43%. Across the temperature range of –40 °C to 125 °C， the minimum temperature coefficient of the output reference voltage was 1.62 ppm/°C. At 10 Hz， the power supply rejection ratio （PSRR） was 62.6 dB. The reference circuit operated stably with a supply voltage ranging from 1.1 V to 5.0 V.

To achieve high-quality and fast sorting of Tibetan text， it is essential to address the identification of the component elements that constitute Tibetan syllables and prioritize them for sorting. By studying the script structure， grammatical rules， and syllable composition of Tibetan， a component element identification algorithm has been designed that aligns with modern Tibetan syllables while remaining independent of Tibetan syllable grammar. This algorithm has been used to develop a sorting method for Tibetan syllables， which in turn has contributed to the creation of a sorting algorithm for multilingual texts involving Tibetan， Chinese， and English. Experiments have demonstrated that this multilingual sorting algorithm for Tibetan， Chinese， and English mixed texts meets the requirements of modern Tibetan dictionary sorting while achieving higher sorting efficiency.

This article provides a systematic review of the innovative applications of graphene heating films in modern agriculture as well as their key preparation technologies. Regarding fabrication techniques， the paper critically examines the technical routes and applicability of physical methods （mechanical exfoliation， liquid-phase exfoliation）， chemical methods （oxidation-reduction method， chemical vapor deposition）， and printing methods （screen printing， inkjet printing， gravure printing）， highlighting the importance of tailoring process selection to specific application scenarios. At the application level， graphene films demonstrate considerable potential across multiple agricultural domains： in crop production， their lightweight nature and superior thermal management capabilities enable precise temperature control and energy savings in greenhouses， with field tests showing promising results in overcoming challenges such as frost protection for fruit trees and weed management； in livestock breeding， their energy-efficient and uniformly heated insulation systems significantly enhance the care of young animals and improve the environmental conditions of livestock housing； in occupational safety， smart wearable film devices contribute to increased comfort and safety for agricultural workers. Looking ahead， further advancements in graphene films must address key technical challenges， including cost reduction， industrial standardization， and performance stability under complex operational conditions. With continued technological integration and innovation， graphene heating films are poised to play a pivotal role in accelerating the transition toward intelligent and sustainable agricultural systems.

Short-text sentiment analysis faces numerous challenges， such as semantic sparsity， concise expression， and lack of contextual information， which lead to incomplete extraction of sentiment features and subsequently affect classification accuracy. To address these issues， this paper proposes a short-text sentiment analysis method based on the Sparrow Search Algorithm （SSA） optimized Transformer. The method transforms the representation of short texts by constructing a word vector matrix； employs the Transformer model to extract sentiment features and introduces SSA to optimize the model’s hyperparameters； inputs the extracted sentiment features into a fully connected layer + Softmax classifier， and uses a gradient descent algorithm with cross-entropy loss to measure the difference between the predicted sentiment and the true sentiment， thereby accomplishing short-text sentiment analysis. SSA offers advantages such as strong global search capability and fast convergence speed， which effectively optimize the hyperparameters of the Transformer model and enhance model performance. Experimental results showed that the proposed method exhibited lower iterative loss， higher classification accuracy， a better ability to capture sentiment features， and a strong capacity to distinguish different types of sentiments.

Aiming at the bottleneck in the development of domestic high common-mode voltage differential amplifiers， based on the 40 V high-precision complementary bipolar process-compatible metal-film trimming resistor，a ±600 V ultra-high common mode voltage precision differential amplifier is designed. The overall structure of the circuit is mainly composed of a peripheral resistor network and an op amp. Through the feedback structure of the peripheral resistor network， combined with the laser trimming technology of the on-chip integrated metal film resistor， the common mode signal can be attenuated by 60 times while the differential mode signal stays unchanged， so as to accurately detect weak differential signals in a high common mode environment. The input stage of the op-amp adopts super beta NPN transistors to reduce the offset voltage， and the output stage of the op-amp adopts class AB complementary output to improve the output voltage range， while the process adopts high-voltage dielectric isolation technology to realize the normal operation of the device under high-voltage condition. The test data show that when the common-mode input voltage reaches ±600 V，the common-mode rejection ratio reaches more than 90 dB， the gain error is 0.02％，the static current is only 550 μA and the output swing is between -V_s+0.3V and V_s-0.3V.

The amplitude of an input high-frequency signal is detected by the large dynamic logarithmic detector（SDLVA） and outputs a voltage signal whose amplitude has a logarithmic relationship with the input signal’s amplitude. Utilizing this characteristic， the RF SDLVA can be widely used in electronic measurement， reconnaissance， electronic product self-testing and other applications. This paper focuses on the zero-point temperature stability of large dynamic range monolithic integrated logarithmic detectors and proposes a novel circuit structure to perform temperature compensation on the output zero-point for its stability over a wide temperature range， ensuring the input logarithmic dynamic range ≥50 dB at the logarithmic error ≤±3 dB.