Fiber-optic acoustic sensors are a novel type of acoustic detector based on optical principles. They offer excellent characteristics such as immunity to electromagnetic interference， compact size， and high sensitivity， making them widely applicable in fields including marine exploration， industrial non-destructive testing， and medical diagnostics. Depending on the signal modulation mechanism， fiber-optic acoustic sensors are primarily classified into intensity-modulated， phase-modulated， and fiber Bragg grating types. Intensity-modulated sensors are affected by the structural properties of the optical fiber itself， leading to limitations such as relatively low sensitivity， narrow dynamic range， and susceptibility to environmental interference. In contrast， phase-modulated sensors exhibit high detection sensitivity and broad frequency response. Particularly， the Fabry-Pérot interferometric （FPI） type demonstrates a minimum detectable sound pressure of 0.28 μPa/Hz1/2. Due to restrictions in the spectral sideband， fiber Bragg grating sensors show comparatively lower sensitivity， though they offer high structural stability and are suitable for harsh environments such as high temperatures and high pressures. Currently， all types of fiber-optic acoustic sensors are continuously advancing toward miniaturization， higher sensitivity， and improved acoustic coupling efficiency， demonstrating broad application prospects.
Aiming at the limitations of bidirectional applications in reconfigurable field-effect transistors （RFETs） with double-gate structures and complementary source-drain doping， as well as the operational complexity arising from the simultaneous power supply requirement for both the control gate and program gate， a bidirectional highly integrated reconfigurable field-effect transistor with a triple-gate and floating-gate structure and complementary source-drain doping is proposed. The triple-gate structure of the device optimizes symmetry in bidirectional applications. During fabrication， the triple-gate structure eliminates the stringent self-alignment concerns associated with the formation of the control gate in double-gate designs. The floating program gate enables single-gate powered operation， while the non-volatile charge storage characteristic of the floating gate effectively reduces static power consumption. In terms of integration density， the device adopts a U-shaped design to enhance compactness.
A gate-all-around （GAA） based highly integrated single-device inverter is proposed to address the limitations of Moore's Law in traditional field-effect transistor inverters. The device employs an asymmetric bias architecture （with the source connected to VSS for low voltage and the drain connected to VDD for high voltage）， constructing a high Schottky barrier at the conduction band interface between the source and the central silicon region. Carrier transport is achieved through a direct tunneling mechanism （tunneling probability >85%）. Simultaneously， a low Schottky barrier is optimized at the drain-valance band heterojunction， effectively eliminating parasitic hole injection. The GAA structure enables the device to realize the fundamental functionality of an inverter using only a single transistor. Simulations conducted using Silvaco TCAD demonstrate that the design successfully achieves inverter functionality， offering higher integration density and lower power consumption compared to traditional CMOS inverters.
Over the past decade， the rapid development of artificial intelligence， photovoltaic technology， home appliances， and automotive industries in China has significantly driven the growth of chip demand， while also imposing more stringent requirements on chip performance. Particularly in high-voltage operating environments， some chip pins need to transmit signals exceeding the power supply voltage. To address this need， a high-voltage-tolerant electrostatic discharge （ESD） protection circuit is designed. This circuit adopts an innovative dual-gate grounded NMOS （dual-GGNMOS） architecture. The test results showed that the design meets ESD testing standards and provides effective electrostatic protection for high-voltage input pins.
With the rapid development of integrated circuits， low-power system-on-chip （SoC） design methodologies are increasingly favored by engineers. Low-power SoC design approaches can be categorized into three tiers： architecture-level， logic-level， and physical-level. These encompass various aspects such as multiple operational modes， configurable peripherals， manual logic optimization， clock gating， logic and power optimization using electronic design automation （EDA） tools， clock tree design， multi-threshold library selection， power gating， multi-voltage operation， multi-voltage domain implementation， and backup domain design. This serves as valuable technical reference for design engineers.
To minimize the tunnel transistor size for higher integration density， an optimized structure of a novel high-low-high Schottky barrier bidirectional tunnel field-effect transistor （HLHSB-BTFET） based on the high-low-high Schottky barrier conduction mechanism is proposed and validated using Silvaco TCAD simulation software. The device abandons the conventional U-shaped gate structure in favor of a gate-all-around encapsulation， embedding the intermediate metal alloy internally to directly adjust the channel position. Its effective channel length is no longer directly determined by the distance between the source/drain and the intermediate metal but depends on the height of the insulating layer between the source and drain. This novel HLHSB-BTFET structure features a significantly reduced device size. Simulation results demonstrate that the optimized transistor exhibits almost no degradation in on-state current while achieving a substantial reduction in volume.
To support the development of the national standard for Chiplet interconnect interfaces and conduct technical validation， this study focuses on verifying the physical layer architecture design of the Chiplet interconnect based on the hierarchical die-to-die （D2D） interface transmission protocol proposed in the national standard "Specification for Chiplet Interconnect Interface （Draft）." The research employs Verilog hardware description language to develop a behavioral-level model of the physical layer for the Chiplet interconnect protocol and completes simulation and verification. The study concentrates on the data processing mechanisms of the transmitter （TX） and receiver （RX）， analyzing the implementation principles and performance of both NRZ and PAM3 encoding schemes. Through waveform simulation experiments， the timing alignment characteristics of TX and RX under NRZ and PAM3 modes are validated， ensuring the accuracy and reliability of data transmission. Additionally， the serial-to-parallel conversion logic of TX and the multi-level decision mechanism of RX are implemented. Finally， the physical layer architecture design is synthesized using Vivado. The results demonstrate that the proposed behavioral model of the physical layer effectively supports the functional requirements of the Chiplet interconnect protocol， with a 11% reduction in latency and a 33% reduction in power consumption. This study provides an experimental basis for the design and optimization of high-performance Chiplet interconnect architectures and offers valuable insights for research and engineering applications in related fields.
With the rapid development of integrated circuit manufacturing processes， new challenges continue to emerge， as many fundamental device components increasingly fail to meet the high demands of modern IC design. In response to the limitations of conventional diodes in certain applications， researchers have proposed a novel Schottky barrier diode with resettable conduction types and non-volatile characteristics. This design utilizes a programming gate to inject charge into a floating gate， enabling the device to maintain its conduction type for extended periods even without power， thereby achieving low static power consumption and reduced reverse leakage current. This innovation not only enhances device efficiency but also offers new solutions for future IC design by improving integration density and reducing chip area.
Outlier detection in data stream environments is a significant issue in stream data management and analysis， with broad applications. Distance threshold-based methods determine whether an object in a window is an outlier. For any object o in the window， if the number of objects within a distance threshold r is fewer than the object count threshold k， then o is considered an outlier. Given the outlier detection parameters q<r，k>， q monitors the objects in the window. As the window slides， the algorithm returns the outliers within the window. Based on this， a novel index structure—GQDT—is proposed for efficient management of stream data. GQDT is a two-layer index structure， with the first layer being a grid index that probes the degree of data distribution， and the second layer consisting of a quadtree index. In regions with dense data distribution， GQDT further employs a quadtree for indexing to facilitate outlier detection. Compared to traditional grid and quadtree indexing methods， GQDT not only inherits the advantage of the grid index in quickly identifying certain outliers but also accelerates range queries for objects that cannot be directly determined， thereby returning all outliers.
This study employs a fuse trimming circuit programming control method to design a low-dropout regulator （LDO） with fast transient response and high precision. The approach effectively corrects output voltage deviations in the reference module caused by offset factors， while an NMOS transistor is utilized as the pass device to enhance transient response speed. Simulation results demonstrated that the output voltage accuracy remained within ±1% under significant load and bias variations. Across different process conditions， the maximum line regulation was 0.000 353%/V. Within the load current range of 50~3 000 mA， the load regulation was 0.005 5%/A. When the load current increased from 50 mA to 3 000 mA at a slew rate of 1 A/μs， the undershoot voltage was 50 mV with a duration of 1.37 μs. Conversely， when the load current decreased from 3 000 mA to 100 mA at 1 A/μs， the overshoot voltage was 35 mV with a settling time of 2.8 μs. These results meet the design requirements for both high precision and fast transient response.
Aiming at electronic systems susceptible to single-event latch-up effects in space applications， an overcurrent protection module with automatic reconnection capability is designed. This module can be installed between the power supply and the single-event latch-up-sensitive system load. When the system load draws excessive current due to single-event latch-up， the module can play the function of overcurrent protection， cutting off the power supply of the system load， allowing it to recover from the latch-up state. Subsequently， the automatic reconnection function enables the system load to automatically restore power and resume operation. When the overcurrent threshold was set below 260 mA， the error accuracy was controlled within ±18%； when the threshold range was set between 600~1 000 mA， the error accuracy was controlled within ±10%. The automatic reconnection time can be adjusted as required. The module is fabricated using layered stacking and epoxy resin potting technology， with electrical connections between internal substrate layers achieved through metal plating on the module’s sides. The overall dimensions of the module are 15 mm × 15 mm × 12 mm， and it weighs less than 8 g.
The study proposes a bias circuit designed to stabilize the operating point of a low-voltage cascode current mirror. The advantage of this circuit lies in its ability to precisely set the drain-source voltage of the cascode transistor， thereby keeping the transistor operating within the designed region under process， voltage， and temperature （PVT） variations. Simulations based on a 0.18 μm CMOS process show that the current mirror maintains stable operation across a supply voltage range of 2.7 V to 5.5 V and a temperature range of -55 °C to 125 °C， while covering typical （tt）， fast （ff）， slow （ss）， and mixed （fs） process corners.
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