Intelligent human-machine interaction systems enabled by flexible electronics demonstrate superior flexibility and adaptability compared to traditional electronic devices, meeting diverse requirements of human-machine interaction. This paper aims to comprehensively review the current research status of flexible electronics in intelligent human-machine interaction systems, thoroughly analyze the advantages of flexible electronics in the field of human-machine interaction, while summarizing and identifying the opportunities and challenges of flexible electronics in human-machine interaction. Furthermore, it looks into the future development trends of intelligent human-machine interaction systems enabled by flexible electronics, providing solid theoretical guidance for subsequent technological development and practical applications.

To address the problem of existing scheduling rules becoming invalid due to sudden job insertions in dynamic job shop scheduling, this paper proposes a real-time scheduling strategy based on the DQN algorithm from deep reinforcement learning. This method enables real-time adjustment of sche-duling decisions in dynamic environments to maximize overall production efficiency while ensuring timely processing of new jobs. The research constructed a dynamic simulation environment to verify the algorithm's performance under various job insertion scenarios. Results demonstrate that this method exhibits better adaptability and robustness compared to traditional scheduling approaches, providing new insights for solving dynamic job shop scheduling problems.

This paper investigates the fabrication process and performance characteristics of graphene-based flexible temperature sensors. The working mechanism of graphene flexible temperature sensors is first elaborated, followed by an exploration of the sensor unit fabrication method using polydimethylsiloxane as the substrate material and graphene as the conductive medium. Through optimization of graphene paste formulation and screen printing technology, flexible temperature sensing units were successfully fabricated. Subsequently, systematic performance tests were conducted on the sensing units, including resistance-temperature characteristic analysis and temperature cycling stability evaluation. Experimental results demon-strate that the fabricated sensing units exhibit excellent performance in terms of resistance-temperature characteristics and cycling stability, showing potential for industrial-grade applications. This study provides important technical support for the practical application of graphene flexible temperature sensors.

To meet the application requirements of ADC in high-precision conversion and multiplexing scenarios, a two-step incremental Sigma-Delta ADC circuit with chopper stabilization is proposed. The design eliminates quantization noise by adding a conversion stage through hardware reuse to quantize residual voltage, and applies chopper stabilization technique to the first-stage integrators of both conversion stages to reduce the impact of op-amp offset voltage. Simulation results show that under conditions of 1 kHz signal bandwidth, 1.8 V power supply, and input normalized sine wave amplitude of 0.6, the ADC achieves a signal-to-noise ratio of 103.6 dB with an effective number of bits of 16.92, making it suitable for multi-sensor multiplexing and high-precision conversion applications.

To address the challenges of missed detections and decreased accuracy caused by pedestrian occlusion in surveillance scenarios, as well as the difficulty in balancing accuracy and computational complexity in tracking algorithms, this paper proposes the M-YOLOv8 pedestrian detection algorithm by introducing a mask attention network based on YOLOv8. Furthermore, by combining M-YOLOv8 with an optimized DeepSort algorithm and implementing a lightweight person re-identification model, a compre-hensive pedestrian detection and tracking solution is developed. Experimental results demonstrate that the improved algorithm maintains high detection accuracy while reducing computational cost, making it effective for pedestrian detection and tracking tasks in surveillance videos.

This paper investigates the electro-thermal coupling topology optimization based on the SIMP density method. First, a SIMP density model was established, and the physical relationships and optimization objectives in the electro-thermal coupling system were analyzed. During model establishment, key parameters such as material thermal conductivity, electrical conductivity, and convective heat transfer coefficient were considered, and the concept of adaptive filter radius was introduced. The research shows that the choice of density model, the generation and distribution of Joule heat, and the setting of objective functions significantly affect the optimization results. By comparing structures optimized with different filter radii(0.2 mm, 0.4 mm, and 0.8 mm), the effects of various parameters on temperature distribution and structural performance were analyzed. The experimental results demonstrate that appropriate filter radius selection can effectively improve structural performance and reduce temperature standard deviation. This study provides theoretical foundation and practical guidance for the design optimization of electro-thermal coupling systems.

Traditional bearing monitoring methods are constrained by external power sources and complex wiring, increasing installation and maintenance difficulties and rendering them unsuitable for confined or harsh environments. The emerging technology combining flexible sensors and machine learning has significantly enhanced the flexibility, accuracy, and real-time performance of intelligent bearing monitoring, providing novel solutions for bearing monitoring. This paper summarizes the research progress of machine learning and flexible sensors in intelligent bearing monitoring, exploring the working principles of flexible sensors, structural design, and machine learning approaches. It elucidates the significance of intelligent bearing monitoring, analyzes the technological developments in bearing monitoring, and discusses the development trends of intelligent bearings based on flexible sensors, aiming to improve the level of intelligent bearing monitoring.

This paper investigates the effect of strain engineering on the quantum transport properties of phosphorene. Based on the research background and application prospects of phosphorene in flexible electronic devices, first-principles calculations were employed to systematically study the strain modulation mechanism of phosphorene. By establishing electronic transport models under different strain conditions, the influence patterns of strain on band structure, electron density, and density of states were analyzed, thus verifying the significant anisotropic characteristics exhibited by phosphorene under strain in different directions. This research provides a theoretical foundation for the application of phosphorene in flexible electronics and sensors, confirming the important role of strain engineering in modulating the electrical properties of phosphorene.

To address the issue of low power efficiency in charge pumps, a four-stage two-branch charge pump boost circuit with charge recycling structure is designed. The charge recycling switches con- nect voltage plates of boost capacitors at different potentials to achieve charge recovery, improving power efficiency. A cross-coupled voltage boosting circuit provides control signals for high-voltage charge transfer switches, simplifying the circuit structure. Three-phase non-overlapping clocks separately control the high-voltage clock generation circuit and charge recycling switches, preventing charge leakage at nodes during potential changes. Simulation results show that the circuit can output 20.11 V under a 5 V power supply. The maximum power efficiency reaches 44.35% and 51.33% before and after enabling the charge recycling function respectively.

The characteristic of flexible sensors being able to be seamlessly attached to uneven surfaces of the measured object makes them widely applicable in fields such as information, energy, healthcare, national defense, and agriculture. This article describes the preparation of a graphene/polydimethylsiloxane (PDMS) composite material with a positive temperature coefficient of resistance, and developing a flexible temperature sensor using it. The graphene/PDMS sensor exhibits a linear positive resistance temperature coefficient within the temperature range of 15~80 ℃, with a linear coefficient of 0.049. The fitting degree is good, and it has good reproducibility and stability. The resistance fluctuation is small within the range of 0.05%~0.08%, and it can also measure temperature well in high humidity environments. The reliability of flexible thermometers in plant applications has been tested, and it can be foreseen that flexible temperature sensors based on graphene/PDMS can achieve the application of plant leaf temperature measurement, which has great potential in precision temperature measurement in smart agriculture.

To address the mechanical damage issue during direct device fabrication of flexible field-effect transistors on flexible substrates, a fabrication method for flexible organic ferroelectric-gate graphene field-effect transistors based on damage-free transfer is proposed. The micro-nano processing of the device is completely performed on rigid substrates before being transferred to flexible substrates through a liquid-phase method, which can effectively avoid performance degradation caused by stress introduced during device fabrication. Experimental results show that the flexible organic ferroelectric-gate graphene field-effect transistors transferred to PET substrates still maintain typical ferroelectric hysteresis characteristics, with a hysteresis window greater than 20 V. After 1 000 bending cycles, the device's hysteresis window shows only about 14% reduction, demonstrating excellent bending durability of the prepared flexible graphene transistor devices. This research provides research schemes and problem-solving approaches for the deve-lopment of flexible wearable electronic systems.

With the development of modern emergency fire-fighting towards intelligence, multi-func-tionality, and miniaturization, wearable devices need to meet both comfort and lightweight requirements to address uncertainties and diverse scenarios in emergencies. Taking the smart infrared AR firefighting mask as an example, this paper elaborates on its design and implementation methods, and analyzes the pain points in emergency firefighting processes. The paper focuses on the application of key technologies such as flexi-ble electronics, micro-nano integration, multi-modal network communication, and artificial intelligence in wearable firefighting equipment. Research shows that the integrated application of these new technologies can significantly improve the intelligence level and practical performance of firefighting equipment. The research findings provide technical support and innovative ideas for the development of smart emergency firefighting wearable devices.

Addressing the significant impact of path planning on efficiency and coverage in UAV information collection tasks, this paper proposes a path planning method based on the A* algorithm. The method uses the deviation distance from the desired path as a cost function, optimizing calculations to ensure the UAV quickly returns to the desired route. It also employs minimum jerk as the objective function to consider UAV dynamic constraints and enhance trajectory smoothness. Through simulation experiments, the effectiveness of the method has been verified. Results demonstrate that this approach significantly improves trajectory smoothness and information collection completeness, effectively reduces energy loss, extends flight time, thereby enhancing the efficiency of UAV information collection.

To address the issues of requiring two separate instruments for traditional PCR and hybridization methods, as well as the problem of aerosol contamination, this paper presents an integrated nucleic acid PCR amplification and hybridization reactor. The device integrates PCR amplification and hybridization reactions into a single fully-enclosed system, mainly consisting of PCR amplification and hybridization reaction chip module, temperature control module, temperature acquisition and control system, main control board, and peristaltic pump module. Experimental results show that the instrument features simple structure, high temperature control precision, and accurate liquid transfer. It achieves automated control while effectively preventing aerosol contamination, demonstrating promising application prospects.

To address the challenge of diverse defect types and varying defect characteristics on wood surfaces, a wood surface defect detection algorithm based on parameter-adaptive Gaussian Mixture Model is proposed. The algorithm only requires feature extraction from defect-free areas of the wood surface and constructs a detection model to accomplish surface defect identification. To further enhance the algorithm's intelligence, regarding the problem of how to select training sample size and quantity, a parameter-adap-tive training sample selection algorithm based on normal texture features is proposed. Finally, the training samples are selected through the adaptive algorithm, and defect localization on wood surfaces is achieved based on the Gaussian Mixture Model. Experimental results demonstrate that the proposed algorithm can simultaneously detect multiple types of wood surface defects, improving the precision and accuracy of wood surface defect detection, thus showing practical application value.

This study addresses the issue of significant memory resource consumption caused by the traditional lookup table method when frequently computing the arctangent function in applications such as image processing, electronic compasses, and navigation control systems. An improved solution based on the CORDIC algorithm is proposed. By increasing the iteration clock frequency and performing one iteration on both the rising and falling edges of the clock, the computational speed is doubled. Additionally, the algorithm supports adjustable calculations for both q1.15 and q1.31 data formats, significantly reducing hardware resource consumption. Simulation results demonstrate that the improved algorithm ensures computational accuracy while effectively enhancing speed and providing data format flexibility, offering a more efficient solution for related applications.

A Field-Effect Transistor based on complementary dual-doped low source/drain resistance XNOR is proposed. The source and drain adopt N-type and P-type region doping to form complementary ohmic contacts, replacing the traditional Schottky contacts in bidirectional RFET. Two gates are used to control different parts of the channel, with their voltages determining the carrier types in their controlled channel regions. Ohmic contacts reduce energy loss and heat generation, improving device efficiency and reliability. The complementary doping technology significantly increases forward conduction current, reduces on-resistance, and achieves better transmission characteristic consistency when the two gates serve as control gates respectively. This device is more suitable for XNOR logic gates, featuring higher forward conduction current, input consistency, and achieving input interchangeability. Various performance indica-tors and functions are verified through Silvaco TCAD simulation.

The study aims to optimize PID parameter control using self-tuning fuzzy control technology, addressing issues such as complex parameter adjustment and insufficient precision in traditional PID control. By employing fuzzy control rules with error(e) and error change(ec) as inputs, self-tuning of parameters is achieved. The self-tuning fuzzy PID controller is successfully simulated using the Simulink module in MATLAB, and its implementation method in MATLAB is demonstrated. Results show that the controller exhibits fast response, high-precision adjustment, and excellent stability, with no overshoot or oscillation. The research provides an efficient and stable solution for control system design, demonstrating significant practical application value.

Based on the excellent microwave characteristics of flexible liquid crystal polymer substrate, this paper designs and implements a miniaturized triple-band bandpass filter. Through the adoption of three-dimensional layout in multilayer LCP substrate and innovative use of vertical spiral inductors and vertical interdigital capacitor structures, the miniaturization of the filter is achieved. The research focuses on analyzing key technologies of multilayer spiral inductor design and vertical interdigital capacitor design, with an in-depth discussion on the effects of defected ground structures. Test results show that the filter features small size and excellent performance, with high consistency between measurement and simulation results, providing a new technical solution for the development of miniaturized communication systems.

This study focuses on optimizing wireless multi-group multicast communication systems using reconfigurable intelligent surface(RIS) technology to minimize base station transmission power while meeting multicast users' quality-of-service requirements. To address the non-convex optimization problem, an algorithm based on convex optimization theory is proposed. By introducing auxiliary variables and employing successive convex approximation, the problem is transformed into a tractable convex constraint form, which is then solved using alternating optimization and penalty methods. The results demonstrate that the introduction of RIS significantly reduces base station transmission power, achieving an approximately 8 dBm reduction compared to non-RIS schemes, with further power savings as the number of RIS reflective elements increases. The proposed algorithm converges within 10 iterations and reduces transmission power by about 4 dBm compared to non-optimized RIS schemes, validating the effectiveness of RIS and the algorithm in enhancing the performance of multi-group multicast systems.

Aiming at the slow speed of traditional comparators， a high-speed comparator with optional speed is proposed. The comparator applies a rail to rail input structure. The pre-amplification circuit of the high-speed comparator is composed of a two-stage differential amplifier， and the result of the amplifier is fed into a latch circuit to get the comparison result. The latch circuit reduces the comparator delay and increases the comparator speed . In the comparator circuit， a comparator reverse input mode selection circuit， a comparator speed mode selection circuit， a comparator output stage selection circuit， and a comparator lag terminal selection circuit are added. The reverse input of the comparator has eight selection modes， the speed of the comparator has four selection modes， and the lag end of the comparator has four selection modes. The rail-to-rail input structure of the comparator circuit can detect differential mode voltage of 2mV. A multifunctional comparator with rail to rail， optional speed and optional hysteresis end is realized.

This paper proposes a source-drain floating-gate field-effect transistor to address the issue of steep PN junctions in traditional devices at nanoscale. The device utilizes metal-intrinsic silicon contact to form Schottky barriers and incorporates a chargeable programming floating gate. Research shows that in N-type operation mode, when positive voltage is applied to the control gate with positive charges stored in the floating gate, it enhances the electric field strength in the overlap region between gate and source-drain, increasing the on-state current. When reverse voltage is applied to the control gate, the positive charges in the floating gate reduce the electric field strength in the overlap region, decreasing energy band bending and thus reducing reverse leakage current. The device features high on-state current and low reverse leakage, with simple fabrication process at nanoscale, showing promising applications in future integrated circuits.

To enhance the logic density of individual transistors and reduce the number of transistors required for XNOR logic implementation, a novel XNOR logic gate based on a Schottky barrier resettable field-effect transistor is study proposed. The device uses NiSi as the metallic compound for both source and drain terminals, forming similar Schottky barriers between the source/drain electrodes and silicon's conduction and valence bands. Analysis and verification are conducted using Silvaco TCAD software to study the device's transfer characteristics, energy band variations, and carrier concentration distributions under different gate voltages. Results show that this design improves forward conduction current and achieves XNOR logic functionality using only one transistor, increasing semiconductor chip integration density compared to traditional CMOS technology, which has significant technical value for integrated circuit development.

To address the problems of short-channel effects and increased leakage current caused by device size scaling , a Complementary Schottky Barrier Source Reconfigurable Field-Effect Transistor(CSBS-RFET) is proposed. The reconfigurable output current, energy band, and carrier concentration distribution under different gate voltages are investigated and verified through Silvaco TCAD simulation. Experimental results show that the design using undoped semiconductor forming low Schottky barriers with Er and Pt metals can effectively enhance the forward conduction current while significantly reducing the off-state current and power consumption. This device shows promising application prospects in the field of high-speed information processing chips.

In light of the shortcomings of the BSIM3v3 model in modeling high-voltage MOS devices for high-voltage integrated circuits, this study proposes an improved method based on BSIM3v3 by analy- zing the effects of gate-source voltage and substrate-source voltage on source-drain resistance, as well as phenomena such as current quasi-saturation, impact ionization current, high-voltage parasitic transistors, and self-heating effects. By incorporating additional sub-circuits such as voltage-controlled resistors(VCR), voltage-controlled voltage sources(VCVS), and current-controlled current sources(CCCS), a SPICE macro model for accurately simulating high-voltage MOS devices is established. This approach significantly enhances the modeling accuracy of high-voltage MOS devices, providing important implications for the design and simulation of high-voltage integrated circuits.

Based on the CSMC 0.18μm CMOS process， a high-precision RC oscillator is designed， and the temperature compensation technology is carried out by pulse density modulation and sigma-delta modulation technology， which improves the temperature stability of the output frequency. The low-leakage switching capacitor resistor and temperature compensation resistor circuit are designed by using the frequency-locked loop architecture， and the temperature compensation of the resistance is carried out by three-point digital trimming technology. In addition， the integrator circuit uses a chopping technique to suppress the influence of offset voltage on the output frequency accuracy， and the voltage controlled oscillator uses a low temperature coefficient resistor to further improve the temperature stability. The simulation results show that the output frequency of the oscillator can be stabilized at 32MHz at different process angles， the output frequency change rate is less than 0.45% in the temperature range of -40~125°C， and the output frequency change rate is less than 0.25% in the range of 1.6~2V power supply voltage， and the power consumption of the whole system is 89.7μW. Compared with other RC oscillators of the same type， this design combines the advantages of high-frequency output， high accuracy， and low power consumption， and can be used as an on-chip clock reference.

With the rapid development of the semiconductor industry， semiconductor chips are advancing toward miniaturization and high integration， giving rise to system-in-package （SiP） technology. The 5V ferroelectric memory chip based on system-in-package technology， the primary component is a 3.3V-powered ferroelectric memory， whose power supply range has been expanded to 5V without altering its core functionality， enabling compatibility with a broader range of hardware systems. This approach resolves the power supply mismatch issue in memory applications， simplifies FeRAM peripheral circuit design， and enhances ease of use. The specific design covers system analysis and design selection， focusing on known-good-die stacking， package interconnect design， and substrate design， providing a detailed overview of the FeRAM5V_SiP design process. Additionally， simulations and analyses of signal integrity， power integrity， and thermal stress are conducted using Sigrity and Flotherm software. These analyses confirm the design’s feasibility and robustness. Compared to traditional PCBs， the FeRAM5V_SiP achieves a smaller size and higher integration at the same performance level， meeting market demands and providing a viable reference for the design of similar SiP chips.

To address the challenge of detecting low-frequency and randomized covert attacks in com-munication networks and the inefficiency of existing methods, this paper designs a detection algorithm for large-scale data flow covert attacks. The algorithm avoids iterative processes by mining energy consumption features and calculating parameter variation coefficients, constructing a lightweight detection model with optimized packet forwarding monitoring mechanism. Experimental results show that the algorithm can detect covert attacks within 1 second, restore communication signals within 3 seconds, and achieve over 93% scalability. The research provides a new technical solution for enhancing communication network security and demonstrates good application value.

To achieve more accurate joint segmentation of the optic cup and optic disc in the early screening and diagnosis of glaucoma, an improved U-Net convolutional neural network, Seg-UNet, is proposed for the evaluation of the cup-to-disc ratio(CDR). The network employs ResNet50 as the encoding layer to enhance the feature extraction capability of images. A simulated human visual fusion receptive field module is incorporated to increase the network's perception of global information. Drawing on the concept of the High-Resolution Network(HRNet), a multi-scale feature fusion module is designed to inte-grate contextual semantic information. The proposed method is validated and compared using the publicly available REFUGE dataset. The results demonstrate that this method outperforms existing segmentation methods in segmenting the optic cup and optic disc on the REFUGE dataset.

To address the issues of decreased accuracy in traditional channel estimation algorithms and excessive pilot overhead caused by the passive nature and high-dimensional characteristics of RIS in RIS-assisted MU-MISO systems, an efficient and low-cost channel estimation algorithm is designed. By leveraging the common column sparsity between the base station and RIS and the row sparsity of the cascaded channel with joint scaling properties, the dimensionality of the cascaded channel matrix is reduced to decrease pilot overhead. Combining dual-structured sparsity, alternating optimization, and iterative reweighted least squares algorithms, the DS-AO-IRLS algorithm is designed to estimate the cascaded channel. Simulation results show that, when using the same pilot overhead for channel estimation, the proposed algorithm improves channel estimation performance by more than 11.2 dB compared to the Orthogonal Matching Pursuit(OMP) algorithm.

To address the comprehensive challenges posed by the rapid development of smart agricul-

To address the issue of multipath fading in radio monitoring, which causes signal strength fluctuations and reduces localization accuracy, this paper proposes an interference source localization method based on a wireless sensor network. The method first employs regional segmentation clustering to determine the number of interference sources and divide the monitoring area. Sensor nodes are then used to collect signal strength, frequency distribution, and correlation coefficients, while time-stamp information is utilized to calculate signal transmission distances. Finally, real-number encoding and crossover recombination optimize the sensor node population, solving the fitness function to obtain the optimal localization path and effectively avoid severe multipath effect regions. Experimental results demonstrate that the proposed method reduces average localization errors by 11.1% and 9.6% compared to the air-ground cooperative and 3D display methods, respectively, while improving localization speed by 34.4% and 47.3%. Additionally, it achieves an interference source recognition rate exceeding 90%, significantly enhancing localization accuracy and efficiency in complex environments.

Repeated positioning accuracy is an important performance index of some moving object，which is relatively simple measuring method is to use a ruler or tape measure to measure directly and manually，which is difficult to ensure measurement accuracy，and the measurement efficiency is lower，the consistency of multiple measurements is not good，but the cost is lower。Another measurement method is to use an expensive coordinate measuring instrument，the accuracy of this measurement method is very high，and the consistency of repeated measurement is good，but the cost is very high。According to the advantages and disadvantages of the above two measurement methods，the motion model of the object is establish at first，then the mathematical model which is easy to understand and realize is abstracted from the motion model，finally，based on the mathematical model，by means of electronic technology，the displacement laser sensor is selected as the measurement distance means，and the repeated positioning accuracy detection system is designed。This system is simple to operate and the measurement accuracy is higher and has a low cost。

With the rapid development of memory technology， the operating voltage of double data rate synchronous dynamic random memory （DDR） is getting lower and lower. In order to meet the power supply requirements of DDR， a linear regulator with both source and sink current capabilities has been designed， which is compatible with DDR1~DDR4 power supply systems and other power supply system requirements. This chip utilizes the characteristics of dual power supply voltage to reduce static power consumption. The input voltage range of the power supply is 2.5V to 3.3V， and the LDO power supply voltage is adjustable from 1.2V to 2.5V according to the power supply requirements of DDR1~DDR4. This design uses a dual-loop regulator to achieve source and sink currents， and the output voltage is adjustable externally by the application. A low-threshold NMOS push-pull output stage is used to achieve an output voltage of 0.6V， and a GM amplifier is added to support fast transient response. The chip was designed using a 0.35um BCD process，the regulator was simulated under different DDR power supply conditions. The output could follow the input. The static current at no load is approximately 440uA to 700uA. The transient response and stability were simulated under the DDR4 power supply condition. When the load current jumped from 0A to 3A， the output voltage fluctuation is about 50mV. The results show that the circuit meets the application requirements of DDR1 to DDR4.

With the rapid development of modern detection technology， signal acquisition and processing techniques have become increasingly important. Traditional hardware structures that rely on Central Processing Units （CPU） combined with high-precision Analog-to-Digital Converters （ADC） are no longer sufficient to meet the demands of high-speed signal processing. This paper presents the design and implementation of a signal acquisition system based on Field Programmable Gate Arrays （FPGA）. The system leverages the parallel processing capabilities of FPGA to achieve rapid signal acquisition， filtering， and storage， and subsequently transmits the data to a Personal Computer （PC） via a serial port for further analysis. Experimental results demonstrate that the system offers high data acquisition rate and processing speed and accuracy， making it suitable for a variety of high-speed signal acquisition applications.

At present， three phase MOSFET driver system is widely used in the field of new energy vehicle， industrial robot， and smart home equipment. Based on the requirements of high integration and three phase DC motor driver in the equipment systems， a three phase driver circuit with adjustable PWM duty cycle is designed. The circuit designed by commercial 0.25μm high voltage BCD technology， and the PWM duty cycle can be adjusted from 0% to 100% through the SPEED port voltage. When the ambient temperature reaches 165.1℃， the over temperature protection can be triggered. The chip is equipped with built-in PWM modulation module， charge pump circuit， bootstrap monitoring module， over temperature protection module and so on， ensuring the reliability of the circuit in the whole system. The simulation results show that the three phase driver circuit with adjustable duty cycle meets the design requirements.

The power consumption of successive approximation analog-to-digital converter （SAR ADC） is mainly derived from three modules： DAC， comparator and SAR logic. Among them， the energy consumed by DAC capacitor array during charge and discharge is an important factor affecting the overall power consumption of SAR ADC. Therefore， the design of low-power capacitor switch procedure is particularly critical. Traditional V_CM-based capacitor switch procedure is widely used in the design of SAR ADC capacitor switching schemes due to its relatively simple working principle and implementation mode. However， when the comparator results are opposite， the power consumption of switching will increase significantly. To solve this problem， this paper proposes a segmented capacitor split V_CM-based capacitor switch procedure， which can effectively reduce the power consumption of the capacitor switch， and designs a 12-bit 10MS/s low-power SAR ADC based on 65nm LP CMOS technology.

In radio multipath propagation environments， periodic variations in signal intensity can overlap with multipath effect fluctuations， making it difficult for direction-finding and positioning systems to distinguish between normal multipath phenomena and signal source location changes. This often leads to the generation of false information and suboptimal data mining outcomes. To address this issue， this paper proposes a radio monitoring data mining method based on fuzzy C-means clustering. First， wavelet transform is employed to decompose radio signals， and a ridge detection algorithm is used to extract instantaneous frequency features. Subsequently， the fuzzy C-means clustering algorithm is applied to perform preliminary clustering of the instantaneous frequency features， and the clustering results are optimized by incorporating spatial neighborhood information. Finally， the anomaly factor of each cluster is calculated to identify abnormal data points， thereby achieving effective information mining. Experimental results demonstrate that the proposed method significantly enhances data mining speed， resource utilization rate， and coverage rate across multiple experimental scenarios， indicating its practical effectiveness.

At present， MOSFET and IGBT drive systems have been widely applied in aerospace equipment. In response to the anti-radiation reinforcement design requirements of high-voltage power drivers， a high-voltage power driver with anti-nuclear radiation reinforcement has been designed. The design mainly focuses on the anti-radiation reinforcement of digital logic circuits， level conversion circuits， and bipolar circuits in the driver circuit. The circuit is designed using commercial 1.0 μm high-voltage SOI technology. The working range of the high-side floating voltage can reach 600 V， with an anti-total dose capacity of ≥3×10^-3 Gy（Si）， an anti-neutron fluence capacity of ≥1×10^-14 n/cm²， and an anti-instantaneous ionizing radiation dose rate capacity of ≥1×10^-9 Gy（Si）/s. The driving capacity can reach 2 A. After irradiation， the functional and performance indicators of the device meet the system application requirements. Test and experimental results show that this high-voltage SOI power driver circuit meets the design requirements.

With the rapid development of integrated circuit design and manufacturing technology， modern chips are becoming larger and larger in size， more and more complex in function， and more and more highly integrated. The concise and efficient implementation of access， debugging， and programming of the information inside the chip has become a crucial problem to be solved urgently， especially in high - end devices such as CPUs， MCUs. This paper proposes an innovative method of introducing a JTAG module into chip design. This method uses dedicated pins to design the JTAG interface， combines the TAP controller with a synchronous state machine to ensure the stability and reliability of debugging. At the same time， an on - chip debugging unit including multiple functional modules such as a debugging control status register is designed to achieve precise monitoring and debugging of the internal operating state of the chip. Through testing and verification， the JTAG debugging interface functions properly， and the operations of breakpoint setting and cancellation， pipeline operation control， and reading and writing of CPU internal registers and memory in the on - chip debugging unit meet expectations， meeting the JTAG function requirements， effectively improving the development efficiency and providing strong support for the development and application of ultra - low - power microcontrollers.