In view of the problems that the reliability of board-level installation is not considered in the design of CQFP devices in the early stage, such as the large coplanarity difference between leads and porcelain, and the insignificant stress release effect of leads, taking CQFP128 devices as an example, the lead molding design and board-level reliability verification are studied. The material structure, wiring mode and lead forming requirements of CQFP are analyzed in detail, and it is proved by experiments that the formed device has better welding coplanarity. After the vibration test of the whole machine, the reliability of the solder joint is characterized by X-ray, scanning electron microscope and other analysis methods. The study can provide reference for lead forming and reliability verification of similar devices.

Aiming at the problems of low sensitivity and long response time of non-dispersive infrared CH₄ gas sensor, a CH₄ gas sensor based on photoconductive principle is designed. The sensor is mainly composed of PbSe photoconductive infrared detector, signal processing circuit, light source driving circuit and light path gas chamber. By analyzing the relationship between gas concentration and detector output signal, the concentration output relationship equation is fitted to realize the detection function. Through experiments, gases with different concentrations are detected at room temperature. The results show that the output error, minimum detection limit, minimum response time and other parameters of the sensor are good, and the gas can be effectively measured in the range of 1000 cm³/m³.

Based on the investigation of existing products, a design scheme of smart home control system is proposed. The design adopts STM32 as the main node and is equipped with Wi-Fi network module to realize the communication between the main controller and Android application. With the help of MQTT protocol, data transmission and message processing are carried out. Through the LVGL graphic UI library installed in the touch screen of LCD serial port, a concise interactive interface is realized, so that users can control household equipment more conveniently. Various sensor technologies are used to collect indoor environmental data in real time and process and analyze them. The design can set different intelligent control strategies for different application scenarios in different time periods, realize automatic home control, and ensure the data and privacy of users by using data encryption and user authentication. The system gives full play to the advantages of modular design and has a good price-performance ratio.

This paper investigates the effect of strain engineering on the quantum transport properties of phosphorene. Based on the research background and application prospects of phosphorene in flexible electronic devices, first-principles calculations were employed to systematically study the strain modulation mechanism of phosphorene. By establishing electronic transport models under different strain conditions, the influence patterns of strain on band structure, electron density, and density of states were analyzed, thus verifying the significant anisotropic characteristics exhibited by phosphorene under strain in different directions. This research provides a theoretical foundation for the application of phosphorene in flexible electronics and sensors, confirming the important role of strain engineering in modulating the electrical properties of phosphorene.

In order to solve the problem that the production cost of integrated circuits increases with the progress of semiconductor manufacturing technology, especially for the problems of large area, high power consumption and poor stability of resistors, capacitors and operational amplifiers in traditional analog architecture DC/DC converters, a buck DC/DC converter based on digital PWM modulation is designed. The design is based on CSMC 0.18 μm BCD process, and the digital PID compensator is designed with Verilog hardware description language, which is verified by simulation in the mixed simulation environment of VCS+XA. The simulation results show that the output ripple is low and the output voltage is stable under different PVT conditions and different loads, and the design goal of low cost and high robustness is realized.

Aiming at the problem that the traditional dynamic element matching(DEM) method needs more hardware resources, a second-order error feedback noise-shaping SAR ADC is designed. The design uses segmented capacitors to reduce the size of DAC array and the capacitance of error feedback loop, and reduce the area of the whole circuit. On this basis, a DEM method applied to segmented capacitor array is formed, which reduces the influence of capacitor mismatch on performance parameters such as signal-to-noise-distortion ratio(SNDR) at the cost of fewer additional circuit components. The simulation results show that the designed noise-shaping SAR ADC can achieve 70.9 dB SNDR with an 8-bit capacitor array with a capacitance mismatch of 0.3%, and the required area is only 0.019 mm².

Intelligent human-machine interaction systems enabled by flexible electronics demonstrate superior flexibility and adaptability compared to traditional electronic devices, meeting diverse requirements of human-machine interaction. This paper aims to comprehensively review the current research status of flexible electronics in intelligent human-machine interaction systems, thoroughly analyze the advantages of flexible electronics in the field of human-machine interaction, while summarizing and identifying the opportunities and challenges of flexible electronics in human-machine interaction. Furthermore, it looks into the future development trends of intelligent human-machine interaction systems enabled by flexible electronics, providing solid theoretical guidance for subsequent technological development and practical applications.

Based on the existing products, a high-precision, low-noise and low-dropout linear voltage regulator circuit is designed. A folded cascode amplifier is designed to reduce noise and improve gain. The PMOS transistor is used to replace the resistor in the overheat protection circuit, which reduces the power consumption. At the same time, the gate drive structure and current control mode are used to realize the turn-on and turn-off of the switch tube. Based on TSMC 0.35 μm BiCMOS process and Cadence software, the design, layout drawing and pre- and post-simulation are carried out, and the relevant parameter values are obtained in the post-simulation. The parameters are analyzed in detail, and the power supply voltage rejection ratio at different frequencies is compared. The experimental results show that the design has achieved the design goal of high precision and low power consumption.

To achieve higher signal-to-noise ratio and area efficiency with limited hardware overhead, a dynamic zoom ADC based on time-division multiplexed SAR ADC is proposed. Meanwhile, a passive implementation scheme for extracting coarse quantized analog residues and feedforward is proposed, which does not require the design of an active summing operational amplifier, avoids the attenuation of common passive summing signals, and reduces the "fuzz" caused by coarse quantization noise leakage. The overall circuit is designed in two parts:coarse quantization and fine quantization. Coarse quantization is realized by a 3 bit asynchronous SAR ADC, and fine quantization is realized by a second-order 3 bit sigma-delta mo-dulator. Based on 0.18 μm CMOS technology, 3.3 V supply voltage, 1 MHz sampling frequency, and 1 kHz bandwidth, the current consumption is 76 μA, and the specific values of signal-to-noise distortion ratio and FOM are obtained, verifying the feasibility of the design.

This study addresses the issue of significant memory resource consumption caused by the traditional lookup table method when frequently computing the arctangent function in applications such as image processing, electronic compasses, and navigation control systems. An improved solution based on the CORDIC algorithm is proposed. By increasing the iteration clock frequency and performing one iteration on both the rising and falling edges of the clock, the computational speed is doubled. Additionally, the algorithm supports adjustable calculations for both q1.15 and q1.31 data formats, significantly reducing hardware resource consumption. Simulation results demonstrate that the improved algorithm ensures computational accuracy while effectively enhancing speed and providing data format flexibility, offering a more efficient solution for related applications.

Aiming at the equalization protection of lithium batteries, a voltage sampling circuit based on the equalization protection chip for lithium batteries is designed. The lithium battery equalization protection adopts the active equalization method. The voltage sampling circuit samples the voltage of two lithium batteries to monitor the difference between lithium batteries, and converts the data through an 8-bit successive approximation digital-to-analog converter. The equalization control logic is used to analyze the converted data and performs equalization protection for the lithium battery. The HHNEC 0.18μm BCD process is used for the design and verified by simulation. Simulation results show that the voltage sampling circuit has high voltage sampling accuracy, and the effective number of bits of the successive approximation type digital-to-analog converter and other indicators have excellent performance. It can reliably sample the voltage of each battery and is suitable for the application of lithium battery equalization protection chip, which is conducive to prolonging the use of battery packs.

In many fields, the mode of FPGA debugging and programming using traditional USB-JTAG interface is greatly limited, for example, due to the long transmission distance, the debugging interface is sealed by the shell and other reasons, it can not operate normally, and each operation can only be directed at a single FPGA, which is inefficient. To solve the problems, a remote debugging and programming system of FPGA based on 32-bit MCU is proposed. The design realizes the remote debugging and programming functions of FPGA through Ethernet. The main control chip is integrated on the FPGA board, and is connected with the FPGA through JTAG and SPI interfaces, and the other end is connected with computer equipment through Ethernet to realize remote debugging and programming functions. The design increases the convenience of FPGA debugging, improves the efficiency of programming, and has strong expansibility.

To address the low-frequency noise interference issue in programmable gain instrumentation amplifiers(IAs) for sensor AFEs, a low-noise programmable gain chopper current-feedback IA is designed. The design employs chopper technology to suppress low-frequency noise, exemplified by 1/f noise. A digital-to-analog converter(DAC) is incorporated to implement sensor offset compensation using current stacking, resolving the issue of performance degradation caused by sensor offset. A programmable resistor network is employed to achieve programmable gain amplification, enhancing the IA's versatility. The IA is based on TSMC's 0.18 μm process, with a supply voltage of 2.7~3.6 V. By adjusting the resistor network, a gain of 16~2048 can be achieved. Additionally, it is also ideal in sensor offset compensation range and equivalent input reference noise parameters.

Aiming at the problem of deterministic delay in stability, reliability and repeatability of high-speed analog-to-digital converter JESD204B interface multi-chip synchronization system, a solution scheme is proposed. Based on the synchronization principle of subclass 1, the scheme can automatically correct the repeatable deterministic delay by automatically correcting the setup and hold time of reference clock relative to the device clock and using the deterministic delay principle. The technology of adjustable SYSREF delay and automatic correction of internal detection mechanism of analog-to-digital converter is adopted to determine the optimal delay time and realize fixed phase sampling of multi-chip analog-to-digital converter. At the receiving end of the programmable logic chip, the relative position of data arrival with the local multi-frame clock is automatically corrected, thus establishing a stable and repeatable deterministic delay. The design is helpful for multi-chip synchronization system to better cope with harsh environment and self-sensitive delay changes.

Traditional Dickson structure charge pumps suffer from slow rise times, which can hinder the performance of antifuse FPGAs in user mode and lead to timing issues. To address these limitations, a rapid-boot charge pump circuit is proposed, building upon the traditional Dickson structure. The enhanced design incorporates a clock signal enhancement circuit and a 0 V generation circuit alongside the standard oscillator, non-overlapping clock generation circuit, and main charge pump circuit. The clock signal en- hancement circuit expedites charge transfer, enabling rapid charge pump boost. The 0 V generation circuit effectively isolates the high-voltage module from the low-voltage module, providing circuit protection during programming mode. Simulation experiments conducted under global equivalent load conditions, based on CMOS technology, demonstrate that the improved charge pump achieves a stable output 57.6% faster than the original design. Actual chip fabrication and circuit function testing confirm the successful implementation of the proposed design.

In view of the critical role of analog-to-digital converter(ADC) in the field of chip and mixed-signal processing, a sigma-delta ADC based on Mash2-1 cascade architecture is designed to explore the possibility of further improving the accuracy of ADC and meet the new requirements of contemporary application systems. TSMC 180 nm CMOS process is adopted in the design. While completing the modulator circuit, Verilog code is used to realize the matching error elimination and digital decimation filter. The modulator is modeled and the non-ideal factors are analyzed, and the non-ideal of the circuit is optimized by using chopper modulation technology. The simulation results show that the design has excellent signal-to-noise ratio and ideal performance indexes such as total harmonic distortion under 3.3 V power supply, 27 ℃ working environment and TT typical process conditions, and is suitable for high-precision and low-distortion applications.

Aiming at the problems existing in the field test of industrial control buses in engineering monitoring, in order to simplify the carrying capacity of equipment and improve the adaptability of monitoring to complex application scenarios, a data integrated monitoring system based on FPGA, connected to the upper computer through PCIe and supporting IIC and SPI buses is proposed. Firstly, the overall design of the integrated monitoring system is given, and then the detailed design schemes of hardware and logic are given according to the principles of hardware reconfigurablity and software field definition. Eight paths of IIC and SPI are designed to meet the problem of excessive industrial monitoring equipment. Hardware interfaces are reduced and software protocol options are increased. According to the requirements, the top-down design module is analyzed and divided to complete the code design. According to the fault-tolerant ability, the monitoring and fault injection functions are designed, the board-level debugging is carried out, and the upper computer test is finally completed. The results show that the designed communication board is qualified and passed the overall verification.

In order to solve the problems of high loss, short service life, poor anti-vibration ability and low reliability of the existing incremental encoder controlled by shaft handle, a design scheme of incremental photoelectric encoder with optical-mechanical-electrical integration is introduced, including innovative designs such as 32-inner petal shaft sleeve and retractable ball positioning, Z-shaped light-shielding disc design and infrared photosensitive OC open-circuit output circuit. Through precise struc-tural design and material selection, high-precision 32-gear electrical signal conversion is realized. The structural reliability is verified by three-dimensional modeling and finite element analysis. By comparing with the technical indexes of foreign similar products, the data and the environmental adaptability are verified. The study has advantages in performance, structure and cost, and has broad application prospects.

A subdivision stepper motor driver is designed based on ARM processor MM32SPIN0280. The main features include external MOS transistor driver, half-bridge driving circuit and current acquisi-tion circuit, which realizes current loop control of motor. The attenuation mode, current sampling time and constant torque vector control method of stepper motor are analyzed in detail. The functions of bootstrap circuit and driving resistor are expounded and quantitatively calculated, which provides theoretical basis for practical circuit design. The design of PWM output and sampling time and the realization method of constant torque vector control are discussed for software. Through the actual motor coil current measure-ment, the advantages of high subdivision drive for constant torque and small current fluctuation are demon-strated. By comparing the current waveforms in the case of 16 and 2 subdivisions, it is proved that the motor torque is more stable and the noise is less when running in high subdivision. The design provides a valuable reference for the development of miniaturized and high-performance stepper motor drivers.

To address the issue of rain streaks remaining due to the poor extraction of rain line features by existing image deraining algorithms, an image deraining network based on dense hybrid attention and global compensation is proposed. Shallow features of the input rainy image are extracted through multi-layer convolution operations. By integrating the advantages of dense connections and residual networks, a dense residual attention module is designed by introducing multiple attention mechanisms to achieve feature recycling and capture multi-scale features of the image. A global compensation module is added to ensure the comprehensiveness of feature extraction. Features are reconstructed through convolutional layers to obtain a clear and rain-free image. Experimental results show that the proposed algorithm outperforms existing classical and novel algorithms, effectively removing rain streaks and enhancing the overall visual quality of the image.

To enhance user experience by reducing the computational complexity of background removal methods in real-time image recognition, a lightweight background removal method based on channel calculations is proposed. The study revolves around the concept and related properties of channel calculations. By utilizing the relationship between the channels of a color image, the selection of target pixels can be achieved through simple arithmetic and relational calculations, avoiding the use of more complex computational forms such as spatial distance formulas and gradients. This effectively reduces computational complexity. Both theoretical and experimental results demonstrate that under application scenarios where the foreground main color is single, the proposed method can select target pixels with low computational complexity and efficiently achieve background removal. This can contribute to improving user experience in real-time intelligent applications related to image processing.

In order to reduce the influence of uneven brightness and dark image and large gray difference between bleeding spots on the detection results of retinal bleeding spots, a retinal bleeding spot detection algorithm based on zero threshold of gray amplitude histogram and regional feature analysis is proposed. The algorithm realizes the shadow correction of the image through the large-scale median filter, and suppresses the background interference points by combining the concave-convex line segments to complete the pre-processing operation. Automatic threshold segmentation of dark targets is carried out by the first zero point in the amplitude histogram of each row and column, and the continuity of blood vessels is improved based on the region growth of amplitude characteristics. According to the different shapes between blood vessels and bleeding points, blood vessels are removed, and bleeding points are segmented. The test results in DIARETDB1 public gallery verify the effectiveness of the algorithm.

Based on the excellent microwave characteristics of flexible liquid crystal polymer substrate, this paper designs and implements a miniaturized triple-band bandpass filter. Through the adoption of three-dimensional layout in multilayer LCP substrate and innovative use of vertical spiral inductors and vertical interdigital capacitor structures, the miniaturization of the filter is achieved. The research focuses on analyzing key technologies of multilayer spiral inductor design and vertical interdigital capacitor design, with an in-depth discussion on the effects of defected ground structures. Test results show that the filter features small size and excellent performance, with high consistency between measurement and simulation results, providing a new technical solution for the development of miniaturized communication systems.

This paper investigates the fabrication process and performance characteristics of graphene-based flexible temperature sensors. The working mechanism of graphene flexible temperature sensors is first elaborated, followed by an exploration of the sensor unit fabrication method using polydimethylsiloxane as the substrate material and graphene as the conductive medium. Through optimization of graphene paste formulation and screen printing technology, flexible temperature sensing units were successfully fabricated. Subsequently, systematic performance tests were conducted on the sensing units, including resistance-temperature characteristic analysis and temperature cycling stability evaluation. Experimental results demon-strate that the fabricated sensing units exhibit excellent performance in terms of resistance-temperature characteristics and cycling stability, showing potential for industrial-grade applications. This study provides important technical support for the practical application of graphene flexible temperature sensors.

To reduce the impact of offset voltage and noise on traditional bandgap references, a low temperature drift, low noise, high-precision voltage bandgap reference is proposed using SMIC 40 nm CMOS process. Temperature coefficient modulation resistors and output voltage divider resistors are trimmed using resistor matrices to minimize the process impact on temperature coefficient and bandgap reference voltage. Chopper modulation combined with a low-pass filter is employed to significantly reduce the influence of offset voltage and noise on the reference voltage. Simulation using Cadence Spectre tools shows that with a 3.3 V power supply under typical conditions, the temperature coefficient of the output voltage is 5.87×10^-6/℃ over a temperature range of -40 ℃ to 125 ℃. After incorporating the chopper circuit, noise is significantly reduced compared to ordinary bandgap references, and relative accuracy is improved by 50 times.

To meet the low-noise and low-offset requirements of analog front-end detection circuits, a programmable gain amplifier based on chopper stabilization technique fabricated using 0.18 μm CMOS process is introduced. The chopper stabilization technique is employed to reduce offset and low-frequency 1/f noise, while the programmable gain stage is used to improve the utilization of the analog front-end cir-cuit's output swing, meeting detection needs in various environments. The amplifier's equivalent input noise integral value from 1 Hz to 10 kHz is 1.43 μV, and it achieves an op-amp input impedance of 4.52 GΩ using an impedance enhancement circuit. A C-2C capacitor array is adopted as a variable capacitor array, enabling gain adjustment from 0 to 15 times with a minimum step of 1/64, which has wide application scenarios for low-noise circuits requiring fine-tuned gain adjustment.

To address the issues of poor flexibility and completeness in existing heterogeneous graph neural network models based on metapath pattern modeling, and to further improve the efficiency of heter-ogeneous graph neural network models, a Forward-Reverse Path Ranking algorithm is proposed based on a detailed analysis of existing model principles. The algorithm leverages the superior performance of graph neural networks as a deep learning-based graph representation technique in extracting graph data features, and can automatically identify and rank metapath patterns in heterogeneous graphs. Through experiments, comparative analyses are conducted with existing models capable of extracting metapath patterns from heterogeneous graphs on commonly used open-source heterogeneous graph datasets, verifying the effective-ness of the algorithm.

The study aims to optimize PID parameter control using self-tuning fuzzy control technology, addressing issues such as complex parameter adjustment and insufficient precision in traditional PID control. By employing fuzzy control rules with error(e) and error change(ec) as inputs, self-tuning of parameters is achieved. The self-tuning fuzzy PID controller is successfully simulated using the Simulink module in MATLAB, and its implementation method in MATLAB is demonstrated. Results show that the controller exhibits fast response, high-precision adjustment, and excellent stability, with no overshoot or oscillation. The research provides an efficient and stable solution for control system design, demonstrating significant practical application value.

To meet the application requirements of ADC in high-precision conversion and multiplexing scenarios, a two-step incremental Sigma-Delta ADC circuit with chopper stabilization is proposed. The design eliminates quantization noise by adding a conversion stage through hardware reuse to quantize residual voltage, and applies chopper stabilization technique to the first-stage integrators of both conversion stages to reduce the impact of op-amp offset voltage. Simulation results show that under conditions of 1 kHz signal bandwidth, 1.8 V power supply, and input normalized sine wave amplitude of 0.6, the ADC achieves a signal-to-noise ratio of 103.6 dB with an effective number of bits of 16.92, making it suitable for multi-sensor multiplexing and high-precision conversion applications.

To address the issue of low power efficiency in charge pumps, a four-stage two-branch charge pump boost circuit with charge recycling structure is designed. The charge recycling switches con- nect voltage plates of boost capacitors at different potentials to achieve charge recovery, improving power efficiency. A cross-coupled voltage boosting circuit provides control signals for high-voltage charge transfer switches, simplifying the circuit structure. Three-phase non-overlapping clocks separately control the high-voltage clock generation circuit and charge recycling switches, preventing charge leakage at nodes during potential changes. Simulation results show that the circuit can output 20.11 V under a 5 V power supply. The maximum power efficiency reaches 44.35% and 51.33% before and after enabling the charge recycling function respectively.

In order to break through the limitation of output capacitor selection and ensure fast load transient response of the converter, based on two control modes of adaptive constant on-time control, a synchronous buck DC/DC converter is proposed, which can select the control mode according to the output capacitor type. In D-CAP mode, capacitors with appropriate equivalent series resistance are supported as output capacitors. In current mode, ceramic capacitors with low equivalent series resistance are supported as output capacitors. Based on the 0.35 μm BCD process, the transient simulation of the converter is carried out by Cadence software. The results show that the design has fast transient response in both modes.

To address the mechanical damage issue during direct device fabrication of flexible field-effect transistors on flexible substrates, a fabrication method for flexible organic ferroelectric-gate graphene field-effect transistors based on damage-free transfer is proposed. The micro-nano processing of the device is completely performed on rigid substrates before being transferred to flexible substrates through a liquid-phase method, which can effectively avoid performance degradation caused by stress introduced during device fabrication. Experimental results show that the flexible organic ferroelectric-gate graphene field-effect transistors transferred to PET substrates still maintain typical ferroelectric hysteresis characteristics, with a hysteresis window greater than 20 V. After 1 000 bending cycles, the device's hysteresis window shows only about 14% reduction, demonstrating excellent bending durability of the prepared flexible graphene transistor devices. This research provides research schemes and problem-solving approaches for the deve-lopment of flexible wearable electronic systems.

The characteristic of flexible sensors being able to be seamlessly attached to uneven surfaces of the measured object makes them widely applicable in fields such as information, energy, healthcare, national defense, and agriculture. This article describes the preparation of a graphene/polydimethylsiloxane (PDMS) composite material with a positive temperature coefficient of resistance, and developing a flexible temperature sensor using it. The graphene/PDMS sensor exhibits a linear positive resistance temperature coefficient within the temperature range of 15~80 ℃, with a linear coefficient of 0.049. The fitting degree is good, and it has good reproducibility and stability. The resistance fluctuation is small within the range of 0.05%~0.08%, and it can also measure temperature well in high humidity environments. The reliability of flexible thermometers in plant applications has been tested, and it can be foreseen that flexible temperature sensors based on graphene/PDMS can achieve the application of plant leaf temperature measurement, which has great potential in precision temperature measurement in smart agriculture.

With the rapid development of IC technology, high-voltage power drive cir cuits have been widely applied in fields such as industrial and automotive electronics. To deeply understand, develop, and master advanced BCD process technology, and to better leverage its advantages in integrating Bipolar, CMOS, and DMOS processes, this paper introduces the characteristics and development history of the BCD process. Combined with the design of 600 V high-voltage power drive circuits, it conducts in-depth research on key technologies including isolation, high-voltage MOS, and layout design. This research can provide effective support for the design and implementation of high-voltage power drive circuits. In the current trend of chip localization in China, it holds significant importance for enhancing the country's integrated circuit design and manufacturing capabilities.

To address the increased difficulty in data mining caused by complex multi-dimensional data features in smart classrooms, and to improve the recall rate, precision, and efficiency of data mining, a multi-dimensional data mining method for smart classrooms based on the Random Forest algorithm is proposed. The method utilizes cloud platforms, educational administration platforms, and other platforms as sources for multi-dimensional data in smart classrooms, collecting relevant data and preprocessing it to eliminate anomalies and highly similar data. Based on the preprocessing results and chi-square test principles, multiple dimensional features related to smart classrooms are selected from the data. Multi-dimensional data mining is then conducted using the selected features and the Random Forest algorithm. Experimental results demonstrate that the proposed method exhibits good performance, significantly improving the accuracy and reliability of data mining.

The application and performance of FDD LTE/NR Dynamic Spectrum Sharing technology in 5G networks is investigated in the study, which focuses on the 1.8 GHz band and conducts experimental tests in an indoor environment. Using drive tests and CQT methods, the study compares network performance under LTE-only, NR-only, and DSS modes. The performance of dynamic spectrum sharing is validated from multiple dimensions, including RSRP, SINR, MCS, occupied RB numbers, and throughput. Results show that while DSS technology improves spectrum utilization, it impacts both LTE and NR performance. LTE performance loss ranges from 3% to 8%, while NR performance loss is between 10% and 22%. DSS technology can flexibly adjust resources based on LTE and NR service demands, and in the context of increasing 5G terminal penetration and network development, can effectively enhance network capacity and spectral efficiency.

To assist relevant departments in better understanding the online public opinion regarding graduate employment, a system for analyzing online public sentiment during the job-seeking period of college graduates has been developed using big data and artificial intelligence technologies. The system is based on the BERT model and collects data from social media using web crawling techniques. After preprocessing the collected data, a sentiment analysis model is trained using deep learning. The model is then integrated into the online public opinion analysis system using front-end and back-end technologies, combining the training results of the model. Currently, the system has been completed and has passed the review of relevant departments. It is about to be put into use, with the expectation of playing a role in overall public opinion control and guidance objectives.

A hardware architecture for 2D discrete wavelet transform(DWT) based on the 5/3 lifting scheme is proposed. The architecture employs a parallel input-output structure for the entire DWT process, using internal RAM to temporarily store intermediate variables during computation. A three-stage pipeline structure is applied to the design of both row and column filters, and a transposition unit with simple logic and small memory is designed. The external RAM storage space is reduced, and 5 RAMs are used to store wavelet coefficients. Through experiments on a XILINX KC705 FPGA, a lossless compression system is implemented, and four images are compressed with compression ratios ranging from 1.3 to 2. The design saves hardware resources, reduces critical path delay, and the DWT module can operate at a frequency of up to 219 MHz, demonstrating certain technical advantages in practical applications.

Using LMS algorithm and FIR frame structure, the implementation method of an adaptive filter system based on FPGA hardware is discussed. The system adopts a top-down modular scheme to design a 16th-order adaptive filter. The top-level file contains five modules: two interfaces, FIR filtering, error measurement and tap coefficient. The system parameters are all verified by MATLAB simulation in the early stage, and the optimal values are selected. The development board with ZYNQ-7000 series chip as the core is selected for the hardware test platform. The noisy sine wave signal is observed by oscilloscope after being filtered by the system, which shows that the denoising effect is good, and the results captured by logic analyzer are in good agreement with the theoretical simulation results from MATLAB. The system can be encapsulated into an adaptive IP core of power amplifier, which is suitable for audio, image, video and other signal filtering processing fields and has certain engineering application value.

Traditional bearing monitoring methods are constrained by external power sources and complex wiring, increasing installation and maintenance difficulties and rendering them unsuitable for confined or harsh environments. The emerging technology combining flexible sensors and machine learning has significantly enhanced the flexibility, accuracy, and real-time performance of intelligent bearing monitoring, providing novel solutions for bearing monitoring. This paper summarizes the research progress of machine learning and flexible sensors in intelligent bearing monitoring, exploring the working principles of flexible sensors, structural design, and machine learning approaches. It elucidates the significance of intelligent bearing monitoring, analyzes the technological developments in bearing monitoring, and discusses the development trends of intelligent bearings based on flexible sensors, aiming to improve the level of intelligent bearing monitoring.