Traditional Dickson structure charge pumps suffer from slow rise times, which can hinder the performance of antifuse FPGAs in user mode and lead to timing issues. To address these limitations, a rapid-boot charge pump circuit is proposed, building upon the traditional Dickson structure. The enhanced design incorporates a clock signal enhancement circuit and a 0 V generation circuit alongside the standard oscillator, non-overlapping clock generation circuit, and main charge pump circuit. The clock signal en- hancement circuit expedites charge transfer, enabling rapid charge pump boost. The 0 V generation circuit effectively isolates the high-voltage module from the low-voltage module, providing circuit protection during programming mode. Simulation experiments conducted under global equivalent load conditions, based on CMOS technology, demonstrate that the improved charge pump achieves a stable output 57.6% faster than the original design. Actual chip fabrication and circuit function testing confirm the successful implementation of the proposed design.

To address the low-frequency noise interference issue in programmable gain instrumentation amplifiers(IAs) for sensor AFEs, a low-noise programmable gain chopper current-feedback IA is designed. The design employs chopper technology to suppress low-frequency noise, exemplified by 1/f noise. A digital-to-analog converter(DAC) is incorporated to implement sensor offset compensation using current stacking, resolving the issue of performance degradation caused by sensor offset. A programmable resistor network is employed to achieve programmable gain amplification, enhancing the IA's versatility. The IA is based on TSMC's 0.18 μm process, with a supply voltage of 2.7~3.6 V. By adjusting the resistor network, a gain of 16~2048 can be achieved. Additionally, it is also ideal in sensor offset compensation range and equivalent input reference noise parameters.