Design and verification of ethernet IP core based on RISC-V architecture

NIE Danfeng, MA Qingyan

MICROPROCESSORS ›› 2025, Vol. 46 ›› Issue (4) : 35-40.

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MICROPROCESSORS ›› 2025, Vol. 46 ›› Issue (4) : 35-40. DOI: 10.3969/j.issn.1002-2279.2025.04.007

Design and verification of ethernet IP core based on RISC-V architecture

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2025, 46(4): 35-40 https://doi.org/10.3969/j.issn.1002-2279.2025.04.007

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